Abstract: The present invention uses a common, hybrid system platform to provide a generalized medical image processing system that can handle the existing medical image application as it is and route the compute intensive medical image processing to a multi-core processor/processing system. The invention allows the processing platform to be shared among healthcare system such as mammography, X-ray, CT Scan MRI, two-photon, laser microscopy, digital pathology, etc. It also allows the processing platform to deliver medical images to a variety of client devices, such as a desktop computer or a handheld device, through the network without high-performance graphical display capabilities because the rendering of the medical images is performed on the Cell BE based platform of the invention.

Abstract: Embodiments of the present invention provide time-varying barcodes for information exchange. Specifically, embodiments of the present invention provide a system and method for communicating information between electronic devices via a time-varying barcode image sequence. In a typical embodiment, information to be transmitted is divided into packets. A barcode image is generated from each packet. Each barcode image is displayed sequentially with varying display times based on the complexity of the barcode image. A second electronic device reads and decodes the barcode image sequence until the entire information is received.

Abstract: The present approach increases bandwidth by performing at least two functions at the pre-processing level. Specifically, under the present approach, program code is structured so that the segmentation and binarization functions/modules (and optionally a blob analysis function/module) are merged into a single module to reduce memory bandwidth. In addition, each image frame is segmented into a plurality of partitions (e.g., vertical strips) to enhance the reusability of the image data in LS already fetched from main memory. Each partition is then processed by a separate one of a plurality of processing engines, thereby increasing the utilization of all processing engines and allowing the processing engines to maintain good bandwidth.

Abstract: Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

Abstract: The present invention allows CPU utilization for a virtual machine (VM) to be captured from a perspective of a host. Specifically, under the present invention, a work request having a set (e.g., one or more) of jobs is received by a host and allocated to a virtual machine on a node. The work request is typically accompanied by an account identifier such as a multi-value billing code. Once the work request is allocated to a particular VM on the node, a “startacct” script is issued, and a first account record is created. Thereafter, the work request is processed and the CPU utilization needed to complete the set of jobs is monitored. Once the set of jobs is completed, an “endacct” script is issued and a second account record is created. Among other things, the second account record includes the monitored CPU utilization and the account identifier.

Abstract: Embodiments of the present invention provide a semiconductor sensor reliability system and method. Specifically, the present invention provides in-situ positioning of a reliability sensor (hereinafter sensors) within each functional block, as well as at critical locations, of a semiconductor system. The quantity and location of the sensors are optimized to have maximum sensitivity to known process variations. In general, the sensor models a behavior (e.g., aging process) of the location (e.g., functional block) in which it is positioned and comprises a plurality of stages connected as a network and a self-digitizer. Each sensor has a mode selection input for selecting a mode thereof and an operational trigger input for enabling the sensor to model the behavior. The model selection input and operation trigger enable the sensor to have an operational mode in which the plurality of sensors are subject to an aging process, as well as a measurement mode in which an age of the plurality of sensors is outputted.

Abstract: Embodiments of the present invention provide a semiconductor sensor reliability system and method. Specifically, the present invention provides in-situ positioning of a reliability sensor (hereinafter sensors) within each functional block, as well as at critical locations, of a semiconductor system. The quantity and location of the sensors are optimized to have maximum sensitivity to known process variations. In general, the sensor models a behavior (e.g., aging process) of the location (e.g., functional block) in which it is positioned and comprises a plurality of stages connected as a network and a self-digitizer. Each sensor has a mode selection input for selecting a mode thereof and an operational trigger input for enabling the sensor to model the behavior. The model selection input and operation trigger enable the sensor to have an operational mode in which the plurality of sensors are subject to an aging process, as well as a measurement mode in which an age of the plurality of sensors is outputted.

Abstract: In general, embodiments of the present invention provide a chip package with multiple TSV configurations. Specifically, the chip package typically includes a backend layer (e.g., metal interconnect layer); a substrate coupled to the backend layer; a set (at least one) of backend side interconnects extending (e.g., angularly) from a side surface of the backend layer to a bottom surface of the backend layer; a set of optional vertical TSVs extending from a top surface of the backend layer through the substrate; and a network organizer positioned in the substrate organizer for handling communications made using the set of backend side interconnects and the set of vertical TSVs. A set of connections (e.g., controlled collapse chip connections (C4s) can be positioned adjacent to any of the vias to provide connectively to other hardware elements such as additional chip packages, buses, etc.

Abstract: This invention describes an apparatus, architecture, method, operating system, data network, and application program products for a hybrid digital system with multiple heterogeneous components. This invention is applied to a multiple generic microprocessor architecture s with a set (e.g., one or more cores) of controlling components and a set of groups of sub-processing components. Under this arrangement, different technology cores and functional components, such as memory, are organized in a way that different technologies can collaborate as a system.

Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. The present invention is further configured to enable processing core and memory utilization by external systems through virtualization.

Abstract: Embodiments of the present invention provide a strong passive ad-hoc radio-frequency identification (RFID) network (the “network). The network typically includes an RFID receiver and N quantity of RFID tags coupled to one another. For example, a network under the present invention can include an RFID reader; a first RFID tag in communication with the RFID reader; and a second RFID tag in communication with the first RFID tag. The first RFID tag and the second RFID tag will have passive capacitance to allow them to store energy and data. In this example, the first RFID tag can be enabled to behave as an RFID reader. Moreover, the first RFID tag is positioned within a first field generated by the RFID reader, while the second RFID tag being in a second field generated by the first RFID tag, the second field generated using the energy stored in the first RFID tag. This type of tag to tag coupling/communication arrangement can continue for a number of tags.

Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. The system is further configured to delegate computational or memory resource needs to a plurality of sub-processing cores for processing to satisfy application demands.

Abstract: In general, embodiments of the present invention provide approaches for providing power to RFID transponders. In one embodiment, the RFID transponder is powered using a magnetic field generated by power lines. In another embodiment, the RFID transponder is powered using a field generated by a wireless network. In the case of the latter, the RFID transponder acts as a member of the wireless network.

Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode.

Abstract: The present invention relates to an imaging-based radio-frequency identification (RFID) transponder. Specifically, the transponder includes a photo-responsive cell for capturing an image; and an analysis component. The photo-responsive cell captures images of objects. Once captured, the analysis component is configured to: determine whether the RFID transponder has sufficient power to analyze the image; analyze the image on the RFID transponder if sufficient power exists; and/or transmit data corresponding to the image to an RFID reader for analysis in the event the RFID transponder has insufficient power to analyze the image. Where quality of the image and/or performance of the transponder are less than desirous, any number of corrective approaches can be taken. For example, the setup of the transponder can be adjusted, the range readout can be reduced, the integration time per pixel of the image can be increased, etc.

Abstract: Embodiments of the present invention provide a computationally-networked unified data bus for a multi-processing domain architecture. Specifically, in a typical embodiment, a unified data bus is provided. A first data bus adapter (e.g., a node) is coupled to the unified data bus (e.g., a link), and a first processing domain is coupled to the first data bus adapter. In general, the first data bus adapter encapsulates, translates, and interprets data communicated between the unified data bus and the first processing domain. In addition, a second data bus adapter (e.g., a node) is coupled to the unified data bus and a second processing domain is coupled to the second data bus adapter. Similar to the first data bus adapter, the second data bus adapter encapsulates, translates, and interprets data communicated between the unified data bus and the second processing domain.

Abstract: A system, method, service and mobile device are disclosed for providing a location of the mobile device. The invention utilizes a mobile phone with a global positioning system (GPS) module which is located in a wireless network. A third party device is able to submit a location query to a mobile telephone service operator (MTSO). This location query includes the mobile phone's telephone number. Using the telephone number, the MTSO determines the base station with which the mobile phone is associated. The location query is then forwarded to the mobile phone via the base station. The mobile phone collects the GPS data from the GPS module and forwards the GPS data to the base station. The base station converts the GPS data to location information and forwards the location information to the third party device via the MTSO.

Abstract: A system, method, service and mobile device are disclosed for providing a location of the mobile device. The invention utilizes a mobile phone with a global positioning system (GPS) module which is located in a wireless network. A third party device is able to submit a location query to a mobile telephone service operator (MTSO). This location query includes the mobile phone's telephone number. Using the telephone number, the MTSO determines the base station with which the mobile phone is associated. The location query is then forwarded to the mobile phone via the base station. The mobile phone collects the GPS data from the GPS module and forwards the GPS data to the base station. The base station converts the GPS data to location information and forwards the location information to the third party device via the MTSO.

Abstract: The system permits sharing both thermographic image processing and visualization across a single universal platform, thus allowing for sharing of processor resources and visualization of thermographic images on a variety of imaging (client) devices without high-performance graphical display cards. In a typical embodiment, a (e.g., medical) thermographic image 2D linear registration algorithm is implemented on a Cell Broadband Engine processor, which has nine processor cores on a chip and has a 4-way SIMD unit for each core. This multi-core processor technological advancement allows for the development of a thermographic image processing system that is used for thermographic image capturing modalities. A platform is used to provide a generalized medical thermographic image capturing and processing system, which handles different types of medical thermographic image apparatuses on a single data processing platform.

Abstract: Under the present invention, it is determined whether sufficient resources exist for deploying a platform dependent application on its specific “native” platform in a grid environment. If not, a platform dependent portion of the application is identified, and the application is split into the platform dependent portion and a platform independent portion. Thereafter, the platform dependent portion is deployed on its corresponding native platform, while the platform independent portion is deployed on another platform in the grid environment based on available resources. Interconnections between the two portions can then be automatically generated. This can include, for example, creating remote method invocation facade interfaces, creating remote method invocation-enabled facade classes, and building a remote method invocation server for the first platform.