Abstract: Disclosed is a solid state dye-sensitized solar cell employing a composite polymer electrolyte, which includes a photoelectrode, a counter electrode, and an electrolyte interposed between the photoelectrode and counter electrode. The electrolyte includes at least one of a middle molecular substance, a polymer mixture, and inorganic nanoparticles, and a redox derivative. The dye-sensitized solar cell reduces crystallinity of the polymer electrolyte to significantly increase ionic conductivity, and enables the polymer electrolyte to smoothly permeate into a titanium oxide layer to improve mechanical properties, thereby significantly increasing energy conversion efficiency. Accordingly, the dye-sensitized solar cell assures high energy conversion efficiency without an electrolyte leak, and thus, it can be stably and practically used for a long time.

Abstract: There is provided a de-interlacing method including: receiving first and third image lines; selecting an upper vector having an N number of pixels among the first image lines, and selecting a lower vector having an N number of pixels among the third image lines; obtaining a weighted value on the basis of a relation between the pixels within the upper vector and a relation between the pixels within the lower vector; selecting an edge direction from the selected upper vector, the selected lower vector, and the obtained weighted value; and interpolating a pixel belonging to a second image line between the first and third image lines on the basis of the selected edge direction.

Abstract: A polishing pad, platen, method of monitoring, method of manufacturing, and method of detecting using a pseudo window area, where the pseudo window area has a thickness less than a thickness of a polishing layer and a thickness greater than zero.

Abstract: Particular aqueous slurry compositions including fine abrasive particles and polishing methods for polishing insulating films such as silicon dioxide and silicon nitride using such slurry compositions are provided in which the abrasive particles have a mean particle surface area of at least about 100 m2/g and the slurry compositions include the abrasive particles and at least one additive selected from potassium hydroxide, sodium hydroxide, ammonium hydroxide and amine compounds.

Abstract: A memory module and a method of packaging memory devices are provided. The method prepares semiconductor packages of the memory devices, each of which has external pins that include data pins and command signal pins, and mounts the packages on a printed circuit board, on which a first bus, a second bus, and a third bus are formed. The data pins of odd-numbered packages and even-numbered packages connect to the first bus and the second bus, respectively. The control signal pins connect to the third bus. Each package can optionally include dummy pins, where the dummy pins of the even-numbered packages and the odd-numbered packages respectively connect to the first and second buses so that each of the first, second and third buses connects to the same number of external pins. The pin assignment of the even-numbered packages can be different from the pin assignment of the odd-numbered packages to facilitate connections of the buses.

Abstract: An additive composition for a slurry contains a first salt of polymeric acid including a first polymeric acid having a first weight average molecular weight and a first base material, and a second salt of polymeric acid including a second polymeric acid having a second weight average molecular weight and a second base material. A slurry composition is prepared by mixing the additive composition, a polishing particle composition, and water. When implementing a chemical mechanical polishing using the slurry composition, a favorable polishing selectivity is realized.

Abstract: A multi in-line module and an electronic component socket for the multi in-line module are provided. One embodiment of a multi in-line memory module includes a printed circuit board having at least two protrusions formed along one edge of the printed circuit board. Each of the protrusions has first and second surfaces for blocks of contact pins. Accordingly, the module can include three or more pin blocks on separate surfaces of the protrusions. The module provides a large number of pins without being significantly larger than a conventional SIMM or DIMM. Alternatively, physical and electrical attachment of multiple circuit boards provides three or more independent pin blocks on the various surfaces of the printed circuit boards. A socket for a module includes dielectric protrusions with two or more gaps between the protrusions and contact pins on side surfaces of the protrusions that are in the gaps.

Abstract: The present invention relates to an apparatus and method for inputting and displaying data for a refrigerator, and more particularly, to an apparatus and method for inputting and displaying data for a refrigerator wherein various data can be inputted and displayed in the form of images using a touchscreen. To this end, in the present invention the input and display of the characters are not made in a manner that the characters for forming the data are inputted but made in the form of the images corresponding to the characters. Thus, the input and display of the data can be performed regardless of the languages, and the regions and countries where the refrigerators are used. Accordingly, the present invention has an advantage in that the information on various data can be conveniently obtained without limitations on the function, used time and language for inputting the characters.

Abstract: A CDMA base station system having increased reliability is disclosed. The base station includes a channel card for modulating/demodulating a transmitted/received signal; a transmitting section for transmitting the signal outputted from the channel card; a receiving section for receiving a remote signal and sending the received signal to the channel card; and a radio frequency (RF) characteristic analyzer, to analyze characteristics of the transmitting section and the receiving section by monitoring output signals thereof and communicating a result to a base station processor. The base station also includes a first processor for interfacing among the channel card, the transmitting section, the receiving section, and the RF characteristic analyzer; a power level measuring device for measuring a power level of a final end of the base station and transmitting the power level to the base station processor; and a second processor for interfacing between the first processor and an exchange.

Abstract: An internal power supply circuit for a semiconductor memory device comprising a differential amplifier having a reference voltage as an input and utilizing an external power supply voltage. An amplifier output provides an internal power supply voltage. The amplifier is connected to a current source which comprises a plurality of transistors connected in series between one side of said amplifier and ground. A current control transistor having a channel larger than the channels of the transistors connected in series is switchable between a first state in which the current control transistor is substantially on and a second state in which said current control transistor is substantially off.

Abstract: A data in/out channel control circuit for a semiconductor memory device with multi-bank structure includes a plurality of split banks each provided with memory cell arrays, each split bank having a plurality of bit line pairs and a sub in/out line pair connected through a column selection transistor pair, for efficiently connecting data from the bit line pairs to a global in/out line pair. The circuit enables transmission of only the data in a given block bank through the global in/out line pair and the sub in/out line pairs with bank selection information and block selection information.

Abstract: An address buffer for a semiconductor memory device having an address input buffer and an address predecoder incorporated together so as to be driven in a single channel, capable of reducing an address predecoding time by a logic combination of outputs of address input buffer, for high speed of operation of a memory device.

Abstract: A substrate bias voltage controlling circuit controls the generation of different substrate bias voltages according to specific modes. A first sensing signal generator is controlled by the substrate bias voltage and generates a first sensing signal when the level of the substrate bias voltage is higher than a predetermined first potential level. A second sensing signal generator is controlled by the substrate bias voltage and a specific mode signal and generates a second sensing signal when the level of the substrate bias voltage is higher than a predetermined second potential level and when the mode signal is enabled.

Abstract: A numerical control method includes the steps of (a) reading an instruction block from a numerical control program; (b) if a predetermined mirror image code is in the instruction block, determining the coordinates of a target location according to the code; (c) adding predetermined interpolation data to the target location coordinates; and (d) moving a tool to the target location to produce the same cutting direction as an original cutting. Thus, uniform machining precision can always be obtained.

Abstract: A low power semiconductor memory device for minimizing power consumption is disclosed. The low power semiconductor memory device includes a memory cell array with a plurality of memory cells connected to a pair of bit lines, and having first and second pairs of data lines each having a normal data line and a complementary data line. The device further includes a first switching circuit for switch-connecting the pair of bit lines to the first pair of data lines in response to column select information and a sense amplifier connected to the pair of bit lines within the memory cell array. A driving circuit transfers external data to one of the normal data line and the complementary data line of the second pair of data lines in response to a write master signal.

Abstract: Disclosed is a DC voltage generating circuit for reducing an electric power consumption in a semiconductor memory device. The DC voltage generating circuit comprises: a refresh counter for setting a refresh cycle; a power source supply controller for logically combining a counting value supplied from the refresh counter and a self-refresh timer driving signal, thereby to generate a power source supply control signal in a refresh section; and a DC voltage generator for generating and supplying a DC voltage through an output terminal of the DC voltage generator, as controlled by the power source supply control signal supplied from the power source supply controller.

Abstract: A tool travel path creating method for a numerical control device comprises the steps of reading G-code program; determining whether or not any correction command is included in the read G-code program; determining whether or not the interior angle between a first vector, being a line segment from a start point of correction to a work starting point, and a second vector, being a line segment from the work starting point to an work ending point, is acute when a correction command is included in the read G-code program, and then creating a tool travel path to be corrected in accordance with the following steps: calculating and storing data for a third vector starting from the work starting point and with a direction perpendicular to the first vector and the same length as the radius of the tool; calculating and storing data for a fourth vector starting from the work starting point and formed by adding the second vector to an intermediary vector with the same direction as the second vector and the same length as