Abstract: A complementary metal oxide semiconductor (CMOS) thin film transistor including a common gate, a logic device including the CMOS thin film transistor, and a method of manufacturing the CMOS thin film transistor are provided. In one embodiment, the CMOS thin film transistor includes a base substrate and a semiconductor layer formed on the base substrate. A PMOS transistor and an NMOS transistor are formed on a single semiconductor layer to intersect each other, and a common gate is formed on the intersection area. In addition, a Schottky barrier inducing material layer is formed on a source and a drain of the PMOS transistor.

Abstract: A defect inspecting apparatus includes a first support unit supporting a standard sample having standard defects, a second support unit supporting a wafer having target defects, a light source irradiating an incident light to the standard sample or the wafer, a light receiving part collecting reflection light reflected from the standard sample and the wafer, a detection part detecting the standard defects and the target defects by using the reflection light, a comparing part comparing information obtained using the reflection light reflected from the standard sample with a predetermined standard information of the standard defects to confirm a reliability of a step for detecting the target defects and a determination portion determining whether the step is allowed to be performed or not.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate having a source region and a drain region, and a gate stack formed on the semiconductor substrate between and in contact with the source and drain regions. The gate stack includes, in sequential order from the substrate: a tunneling film; a first trapping material film doped with a first predetermined impurity, the first trapping material film having a higher dielectric constant than the nitride film (Si3N4); a first insulating film having a higher dielectric constant than a nitride film; and a gate electrode. Such a nonvolatile semiconductor memory device can effectively control the trap density according to the doping concentration, thereby increasing the write/erase speed of data at a low operating voltage.

Abstract: In a method and an apparatus for inspecting a wafer surface, a wafer is loaded into a chamber. An incident light including a first light for sensing a vertical position of the wafer and a second light for inspecting the wafer surface is irradiated onto the wafer. The first light is reflected on an inspection region or a next inspection region of the wafer and is detected to control a wafer position. The second light is scattered on the inspection region and is detected to inspect the wafer surface of the inspection region. Position information of a wafer is examined and a position of the wafer is adjusted before inspecting a surface of inspection region of a wafer so as to enable accurate inspection of the wafer surface.

Abstract: In a method for inspecting a defect in accordance with one aspect of the present invention, an object is divided into a plurality of regions. Reflectivity of each of the plurality of regions is obtained. Amplification ratio for each region is determined using the reflectivity. A light is irradiated onto the regions. A light reflected from a first region is amplified by a first amplification ratio that is determined for the first region. Moving the irradiated light from the first region to a second region is detected. A light reflected from the second region is amplified by a second amplification ratio that is determined for the second region. The amplified lights from the first region and the second region are analyzed to determine an existence of a defect on the object.

Abstract: A SONOS memory device, and a method of erasing data from the same, includes injecting charge carriers of a second sign into a trapping film, which traps charge carriers of a first sign to store data therein. The charge carriers of the second sign are generated by an electric field formed between one of a first and second electrodes contacting at least one bit line and a gate electrode contacting a word line. A blocking film may be provided between the gate electrode and the trapping film. The charge carriers of the second sign may be hot holes. This erasing improves erasing speed, thereby improving performance of the SONOS memory device.

Abstract: In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device, and methods of manufacturing and operating the same, the SONOS memory device includes a semiconductor layer including source and drain regions and a channel region, an upper stack structure formed on the semiconductor layer, the upper stack structure and the semiconductor layer forming an upper SONOS memory device, and a lower stack structure formed under the semiconductor layer, the lower stack structure and the semiconductor layer forming a lower SONOS memory device.

Abstract: A SONOS memory device, and a method of erasing data from the same, includes injecting charge carriers of a second sign into a trapping film, which traps charge carriers of a first sign to store data therein. The charge carriers of the second sign are generated by an electric field formed between one of a first and second electrodes contacting at least one bit line and a gate electrode contacting a word line. A blocking film may be provided between the gate electrode and the trapping film. The charge carriers of the second sign may be hot holes. This erasing improves erasing speed, thereby improving performance of the SONOS memory device.

Abstract: A defect inspecting apparatus includes a first support unit supporting a standard sample having standard defects, a second support unit supporting a wafer having target defects, a light source irradiating an incident light to the standard sample or the wafer, a light receiving part collecting reflection light reflected from the standard sample and the wafer, a detection part detecting the standard defects and the target defects by using the reflection light, a comparing part comparing information obtained using the reflection light reflected from the standard sample with a predetermined standard information of the standard defects to confirm a reliability of a step for detecting the target defects and a determination portion determining whether the step is allowed to be performed or not.

Abstract: Provided is a nonvolatile memory device which includes a tunneling insulating film formed on a semiconductor substrate, a storage node formed on the tunneling insulating film, a blocking insulating film formed on the storage node, and a control gate electrode formed on the blocking insulating film. The storage node includes at least two trapping films having different trap densities, and the blocking insulating film has a dielectric constant greater than that of the silicon oxide film.

Abstract: A complementary metal oxide semiconductor (CMOS) thin film transistor including a common gate, a logic device including the CMOS thin film transistor, and a method of manufacturing the CMOS thin film transistor are provided. In one embodiment, the CMOS thin film transistor includes a base substrate and a semiconductor layer formed on the base substrate. A PMOS transistor and an NMOS transistor are formed on a single semiconductor layer to intersect each other, and a common gate is formed on the intersection area. In addition, a Schottky barrier inducing material layer is formed on a source and a drain of the PMOS transistor.

Abstract: A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.

Abstract: In a method for manufacturing a single electron memory device including a single electron storage element in a gate lamination pattern formed on a nano-scale channel region of a MOSFET, formation of the gate lamination pattern includes sequentially forming a lower layer and a single electron storage medium for storing a single electron tunneling through the lower layer on a substrate, forming an upper layer including a plurality of quantum dots on the single electron storage medium, forming a gate electrode layer on the upper layer to be in contact with the plurality of quantum dots, and patterning the lower layer, the single electron storage medium, the upper layer, and the gate electrode layer, in reverse order.

Abstract: In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device, and methods of manufacturing and operating the same, the SONOS memory device includes a semiconductor layer including source and drain regions and a channel region, an upper stack structure formed on the semiconductor layer, the upper stack structure and the semiconductor layer forming an upper SONOS memory device, and a lower stack structure formed under the semiconductor layer, the lower stack structure and the semiconductor layer forming a lower SONOS memory device.

Abstract: In a method for inspecting a defect in accordance with one aspect of the present invention, an object is divided into a plurality of regions. Reflectivity of each of the plurality of regions is obtained. Amplification ratio for each region is determined using the reflectivity. A light is irradiated onto the regions. A light reflected from a first region is amplified by a first amplification ratio that is determined for the first region. Moving the irradiated light from the first region to a second region is detected. A light reflected from the second region is amplified by a second amplification ratio that is determined for the second region. The amplified lights from the first region and the second region are analyzed to determine an existence of a defect on the object.

Abstract: In a method and an apparatus for inspecting a wafer surface, a wafer is loaded into a chamber. An incident light including a first light for sensing a vertical position of the wafer and a second light for inspecting the wafer surface is irradiated onto the wafer. The first light is reflected on an inspection region or a next inspection region of the wafer and is detected to control a wafer position. The second light is scattered on the inspection region and is detected to inspect the wafer surface of the inspection region. Position information of a wafer is examined and a position of the wafer is adjusted before inspecting a surface of inspection region of a wafer so as to enable accurate inspection of the wafer surface.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate having a source region and a drain region, and a gate stack formed on the semiconductor substrate between and in contact with the source and drain regions. The gate stack includes, in sequential order from the substrate: a tunneling film; a first trapping material film doped with a first predetermined impurity, the first trapping material film having a higher dielectric constant than the nitride film (Si3N4); a first insulating film having a higher dielectric constant than a nitride film; and a gate electrode. Such a nonvolatile semiconductor memory device can effectively control the trap density according to the doping concentration, thereby increasing the write/erase speed of data at a low operating voltage.

Abstract: A SONOS memory device, and a method of erasing data from the same, includes injecting charge carriers of a second sign into a trapping film, which traps charge carriers of a first sign to store data therein. The charge carriers of the second sign are generated by an electric field formed between one of a first and second electrodes contacting at least one bit line and a gate electrode contacting a word line. A blocking film may be provided between the gate electrode and the trapping film. The charge carriers of the second sign may be hot holes. This erasing improves erasing speed, thereby improving performance of the SONOS memory device.

Abstract: A single electron memory device including quantum dots between a gate electrode and a single electron storage element and a method for manufacturing the same, wherein the single electron memory device includes a substrate on which a nano-scale channel region is formed between a source and a drain, and a gate lamination pattern including quantum dots on the channel region. The gate lamination pattern includes a lower layer formed on the channel region, a single electron storage medium storing a single electron tunneling through the lower layer formed on the lower layer, an upper layer including quantum dots formed on the single electron storage medium, and a gate electrode formed on the upper layer to be in contact with the quantum dots.

Abstract: A single electron memory device including quantum dots between a gate electrode and a single electron storage element and a method for manufacturing the same, wherein the single electron memory device includes a substrate on which a nano-scale channel region is formed between a source and a drain, and a gate lamination pattern including quantum dots on the channel region. The gate lamination pattern includes a lower layer formed on the channel region, a single electron storage medium storing a single electron tunneling through the lower layer formed on the lower layer, an upper layer including quantum dots formed on the single electron storage medium, and a gate electrode formed on the upper layer to be in contact with the quantum dots.