Abstract: A data driver includes a digital to analog converter configured to receive a reference gray voltage and image data, and configured to generate gray voltages corresponding to the image data, and an output buffer including a plurality of buffer circuits connected to an output terminal of the digital to analog converter, and configured to selectively receive one of the gray voltages.

Abstract: An electronic device, including a touch recognition unit; a display unit receiving a signal from the touch recognition unit; a fingerprint recognition unit receiving a signal from the display unit. A processor is configured to transmit and receive a signal to/from the touch recognition unit, the display unit, and the fingerprint recognition unit. The processor may remain in an inactive state while the touch recognition unit, display unit, and fingerprint recognition unit are activated. The processor is activated when a preset user's fingerprint input is provided. A method operates the electronic device.

Abstract: A data driver includes a digital to analog converter configured to receive a reference gray voltage and image data, and configured to generate gray voltages corresponding to the image data, and an output buffer including a plurality of buffer circuits connected to an output terminal of the digital to analog converter, and configured to selectively receive one of the gray voltages.

Abstract: A digital-to-analog converter may include a converting unit and a distributing unit. The converting unit may generate a first analog signal set based on less-than-all bits of an image data set in a first period and may generate a second analog signal set based on all bits of the image data set in a second period. The all bits may include at least 2 bits. The distributing unit may include output terminals, may distribute the first analog signal set to the output terminals in a first sequence in the first period, and may distribute the second analog signal to the output terminals in a second sequence. The second sequence may be opposite to the first sequence.

Abstract: A digital-to-analog converter may include a converting unit and a distributing unit. The converting unit may generate a first analog signal set based on less-than-all bits of an image data set in a first period and may generate a second analog signal set based on all bits of the image data set in a second period. The all bits may include at least 2 bits. The distributing unit may include output terminals, may distribute the first analog signal set to the output terminals in a first sequence in the first period, and may distribute the second analog signal to the output terminals in a second sequence. The second sequence may be opposite to the first sequence.

Abstract: A data driver includes a digital to analog converter configured to receive a reference gray voltage and image data, and configured to generate gray voltages corresponding to the image data, and an output buffer including a plurality of buffer circuits connected to an output terminal of the digital to analog converter, and configured to selectively receive one of the gray voltages.

Abstract: A display device is provided. The display device includes: a timing controller and a data driver. The timing controller is configured to receive input data, a main clock signal, a synchronization signal, or a protocol signal, to generate an internal clock signal by using the main clock signal, to convert the input data into image data, and to transmit the synchronization signal or the protocol signal using the internal clock signal. The data driver is configured to recover the synchronization signal or the protocol signal from the internal clock signal, and to drive the image data by using the recovered synchronization signal or the protocol signal.

Abstract: A data driver capable of generating pre-emphasis voltages is provided. The data driver includes a pre-emphasis unit for comparing previous input data signals with current input data signals to generate pre-emphasis data signals, a first register unit for storing the current input data signals from the pre-emphasis unit and for supplying the previous input data signals to the pre-emphasis unit, and a second register unit for storing the pre-emphasis data signals.

Abstract: A coarse lock detector for a delayed locked loop (DLL) is disclosed. The coarse lock detector includes multiple detection cells. Each detection cell receives a delayed clock phase and an output of a previous detection cell as inputs. To increase time for the output of the previous detection cell to propagate, the detection cells are arranged in groups such that the output from the previous detection cell is generated by a detection cell which is more than one detection cell previous.

Abstract: A display device is disclosed. According to some aspects, the display device includes a display panel for displaying an image, data drivers for supplying data signals to the display panel such that the display panel displays an image, and a timing controller for setting the data drivers and 3n (where n is a natural number) ports. The display device is configured to transmit an R transmission signal including R data bits, a G transmission signal including G data bits, and a B transmission signal including B data bits to the data drivers through the 3n ports. According to some aspects, a display device capable of securing a band width required for driving a three dimensional image without unnecessarily increasing ports and without increasing the transmission speed of the ports and a method of driving the same are disclosed.

Abstract: A display device is provided. The display device includes: a timing controller and a data driver. The timing controller is configured to receive input data, a main clock signal, a synchronization signal, or a protocol signal, to generate an internal clock signal by using the main clock signal, to convert the input data into image data, and to transmit the synchronization signal or the protocol signal using the internal clock signal. The data driver is configured to recover the synchronization signal or the protocol signal from the internal clock signal, and to drive the image data by using the recovered synchronization signal or the protocol signal.

Abstract: A coarse lock detector for a delayed locked loop (DLL) is disclosed. The coarse lock detector includes multiple detection cells. Each detection cell receives a delayed clock phase and an output of a previous detection cell as inputs. To increase time for the output of the previous detection cell to propagate, the detection cells are arranged in groups such that the output from the previous detection cell is generated by a detection cell which is more than one detection cell previous.

Abstract: A level-down shifter includes: a first load device between a first voltage and a first node; a second load device between the first voltage and a second node; a first input device between the first node and a third node, receiving a reference voltage signal, and adjusting a first node voltage of the first node based on the reference voltage signal; a second input device between the second node and the third node, receiving an input signal, and adjusting a second node voltage of the second node based on the input signal; and a current source between a second voltage and the third node, receiving the second node voltage of the second node, and adjusting a third node voltage of the third node and a bias current based on the second node voltage of the second node, wherein a level of the input signal is higher than the first voltage.

Abstract: A coarse lock detector for a delayed locked loop (DLL) is disclosed. The coarse lock detector includes multiple detection cells. Each detection cell receives a delayed clock phase and an output of a previous detection cell as inputs. To increase time for the output of the previous detection cell to propagate, the detection cells are arranged in groups such that the output from the previous detection cell is generated by a detection cell which is more than one detection cell previous.

Abstract: A coarse lock detector is disclosed. The course lock detector uses an initial lock range to determine course lock, and once course lock is achieved, uses a modified lock range to determine course lock.

Abstract: A data driver capable of generating pre-emphasis voltages is provided. The data driver includes a pre-emphasis unit for comparing previous input data signals with current input data signals to generate pre-emphasis data signals, a first register unit for storing the current input data signals from the pre-emphasis unit and for supplying the previous input data signals to the pre-emphasis unit, and a second register unit for storing the pre-emphasis data signals.

Abstract: A display device is disclosed. According to some aspects, the display device includes a display panel for displaying an image, data drivers for supplying data signals to the display panel such that the display panel displays an image, and a timing controller for setting the data drivers and 3n (where n is a natural number) ports. The display device is configured to transmit an R transmission signal including R data bits, a G transmission signal including G data bits, and a B transmission signal including B data bits to the data drivers through the 3n ports. According to some aspects, a display device capable of securing a band width required for driving a three dimensional image without unnecessarily increasing ports and without increasing the transmission speed of the ports and a method of driving the same are disclosed.

Abstract: An image display device capable of reducing power consumption. The image display device includes: a position determining unit for determining positions of horizontal lines to which data input to a timing controller are to be supplied; a look-up table (LUT) for storing pre-emphasis voltage information corresponding to the positions of the horizontal lines; the timing controller for transmitting the data and the pre-emphasis voltage information to a data driver; a pre-emphasis voltage generator for generating a pre-emphasis voltage to correspond to the pre-emphasis voltage information from the data driver; and the data driver for supplying the pre-emphasis voltage to data lines in a partial period of a horizontal period and for supplying a data signal in a remaining period of the horizontal period.

Abstract: A coarse lock detector for a delayed locked loop (DLL) is disclosed. The coarse lock detector includes multiple detection cells. Each detection cell receives a delayed clock phase and an output of a previous detection cell as inputs. To increase time for the output of the previous detection cell to propagate, the detection cells are arranged in groups such that the output from the previous detection cell is generated by a detection cell which is more than one detection cell previous.

Abstract: A coarse lock detector is disclosed. The course lock detector uses an initial lock range to determine course lock, and once course lock is achieved, uses a modified lock range to determine course lock.