Patents by Inventor Moon-Sang Hwang

Moon-Sang Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120206185
    Abstract: A level-down shifter includes: a first load device between a first voltage and a first node; a second load device between the first voltage and a second node; a first input device between the first node and a third node, receiving a reference voltage signal, and adjusting a first node voltage of the first node based on the reference voltage signal; a second input device between the second node and the third node, receiving an input signal, and adjusting a second node voltage of the second node based on the input signal; and a current source between a second voltage and the third node, receiving the second node voltage of the second node, and adjusting a third node voltage of the third node and a bias current based on the second node voltage of the second node, wherein a level of the input signal is higher than the first voltage.
    Type: Application
    Filed: January 25, 2012
    Publication date: August 16, 2012
    Inventors: Moon-Sang Hwang, Won-Jun Choe, Hyun-Chang Kim, Deog-Kyoon Jeong
  • Patent number: 7409031
    Abstract: A method and apparatus for 2× oversampling of data having jitter. In some embodiments, the invention is a clock and data recovery device including an alternating edge sampling binary phase detector, and which is configured to stabilize loop characteristics in various jitter environments and can be implemented with small hardware overhead. A transceiver that embodies the invention can be implemented as a CMOS integrated circuit using a 0.18 ?m CMOS process, with the transceiver chip being capable of recovering data having a data rate of up to 11.5 Gbps from a signal received over a serial link, while consuming no more than 540 mW from 1.8V supply, and with a bit error rate of less than 10?12.
    Type: Grant
    Filed: August 15, 2003
    Date of Patent: August 5, 2008
    Assignee: Silicon Image, Inc.
    Inventors: Bong-Joon Lee, Moon-Sang Hwang, Sang-Hyun Lee, Deog-Kyoon Jeong
  • Patent number: 7102446
    Abstract: A phase lock loop (PLL) for controlling a sampling clock or other clock, and a data sampling circuit, transceiver, or other device including such a PLL. The PLL includes a multi-range VCO, at least one fine control loop for controlling the VCO, and a coarse control loop for controlling the VCO by changing its frequency-voltage characteristic. The coarse control loop includes a frequency lock detector and voltage range monitoring logic. Typically, the frequency lock detector locks operation of the coarse control loop when the difference between the VCO output clock frequency and a reference frequency decreases to within a predetermined threshold, and the unlocked coarse control loop employs the voltage range monitoring logic to change the VCO frequency-voltage characteristic when the VCO's fine control voltage leaves a predetermined range.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: September 5, 2006
    Assignee: Silicon Image, Inc.
    Inventors: Hyung-Rok Lee, Moon-Sang Hwang, Sang-Hyun Lee, Bong-Joon Lee, Deog-Kyoon Jeong
  • Patent number: 6819166
    Abstract: In a class of embodiments, an adaptive equalization circuit that implements a joint adaptation algorithm. Other embodiments are receivers that include such an adaptive equalization circuit, and joint adaptation equalization methods. The equalization circuit includes a filter having a low-frequency-gain path (sometimes referred to as a low-frequency filter) and a high-frequency-boosting path (sometimes referred to as a high-frequency filter). The high-frequency filter typically includes a high-pass filter in series with an amplifier having adjustable gain. A high-frequency-boosting tuning loop controls the adjustable gain applied by the high-frequency filter. A low-frequency-gain tuning loop controls the adjustable gain applied by the low-frequency filter.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: November 16, 2004
    Assignee: Silicon Image, Inc.
    Inventors: Jong-Sang Choi, Moon-Sang Hwang, Deog-Kyoon Jeong