Patents by Inventor Morgan D. Evans

Morgan D. Evans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10847372
    Abstract: Methods for processing of a workpiece are disclosed. The actual rate at which different portions of an ion beam can process a workpiece, referred to as the processing rate profile, is determined by measuring the amount of material removed from, or added to, a workpiece by the ion beam as a function of ion beam position. An initial thickness profile of a workpiece to be processed is determined. Based on the initial thickness profile, a target thickness profile, and the processing rate profile of the ion beam, a first set of processing parameters are determined. The workpiece is then processed using this first set of processing parameters. In some embodiments, an updated thickness profile is determined after the first process and a second set of processing parameters are determined. A second process is performed using the second set of processing parameters. Optimizations to improve throughput are also disclosed.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: November 24, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Morgan D. Evans, Kevin Anglin, Ross Bandy
  • Patent number: 10739208
    Abstract: An improved system and method of measuring the temperature of a workpiece being processed is disclosed. The temperature measurement system determines a temperature of a workpiece by measuring the amount of expansion in the workpiece due to thermal expansion. The amount of expansion may be measured using a number of different techniques. In certain embodiments, a light source and a light sensor are disposed on opposite sides of the workpiece. The total intensity of the signal received by the light sensor may be indicative of the dimension of the workpiece. In another embodiment, an optical micrometer may be used. In another embodiment, a light sensor may be used in conjunction with a separate device that measures the position of the workpiece.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: August 11, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Klaus Petry, Jason M. Schaller, Ala Moradian, Morgan D. Evans
  • Patent number: 10600675
    Abstract: A method may include providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising an insulator layer and a silicon layer. The silicon layer may be disposed on the insulator layer, where the silicon layer comprises a first silicon thickness variation. The method may include forming an oxide layer on the silicon layer, where the oxide layer has a uniform thickness. The method may include selectively etching the oxide layer on the silicon layer, wherein the oxide layer comprises a first non-uniform oxide thickness. After thermal processing of the SOI substrate in an oxygen ambient, the non-uniform oxide thickness may be configured to generate a second silicon thickness variation in the silicon layer, less than the first silicon thickness variation.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: March 24, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Andrew M. Waite, Morgan D. Evans, John Hautala
  • Patent number: 10443934
    Abstract: A system for heating substrates while being transported between the load lock and the platen is disclosed. The system comprises an array of light emitting diodes (LEDs) disposed above the alignment station. The LEDs may be GaN or GaP LEDs, which emit light at a wavelength which is readily absorbed by silicon, thus efficiently and quickly heating the substrate. The LEDs may be arranged so that the rotation of the substrate during alignment results in a uniform temperature profile of the substrate. Further, heating during alignment may also increase throughput and eliminate preheating stations that are currently associated with the processing chamber.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: October 15, 2019
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Morgan D. Evans, Jason M. Schaller, D. Jeffrey Lischer, Ala Moradian, William T. Weaver, Robert Brent Vopat
  • Publication number: 20190170591
    Abstract: An improved system and method of measuring the temperature of a workpiece being processed is disclosed. The temperature measurement system determines a temperature of a workpiece by measuring the amount of expansion in the workpiece due to thermal expansion. The amount of expansion may be measured using a number of different techniques. In certain embodiments, a light source and a light sensor are disposed on opposite sides of the workpiece. The total intensity of the signal received by the light sensor may be indicative of the dimension of the workpiece. In another embodiment, an optical micrometer may be used. In another embodiment, a light sensor may be used in conjunction with a separate device that measures the position of the workpiece.
    Type: Application
    Filed: February 21, 2018
    Publication date: June 6, 2019
    Inventors: Klaus Petry, Jason M. Schaller, Ala Moradian, Morgan D. Evans
  • Patent number: 10276340
    Abstract: A system for implanting ions into a workpiece while minimizing the generation of particles is disclosed. The system includes an ion source having an extraction plate with an extraction aperture. The extraction plate is electrically biased and may also be coated with a dielectric material. The workpiece is disposed on a platen and surrounded by an electrically biased shield. The shield may also be coated with a dielectric material. In operation, a pulsed DC voltage is applied to the shield and the platen, and ions are attracted from the ion source during this pulse. Since a pulsed voltage is used, the impedance of the thin dielectric coating is reduced, allowing the system to function properly.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: April 30, 2019
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Morgan D. Evans, Ernest E. Allen, Jr., Tyler Burton Rockwell, Richard J. Hertel, Joseph Frederick Sommers, Christopher R. Campbell
  • Patent number: 10269663
    Abstract: An apparatus of a wafer processing apparatus includes at least one memory and logic, at least a portion of which is implemented in circuitry of the wafer processing apparatus including at least one processor coupled to the at least one memory. The logic may provide a 3D model of a surface of a wafer, the wafer defining a wafer plane; and modify a surface feature in a Z-direction along the surface of the wafer based on at least one of: an X-critical dimension (CD) extending along an X-direction of the wafer plane, and a Y-CD extending along a Y direction of the wafer plane.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: April 23, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Morgan D. Evans, Tristan Ma, Kevin Anglin, Motoya Okazaki, Johannes M. van Meer
  • Patent number: 10222202
    Abstract: An apparatus may include a processor and memory unit, including a control routine having a measurement processor to determine, based upon a first set of scatterometry measurements, a first change in a first dimension of a first set of substrate features along a first direction. The first set of substrate features may be elongated along a second direction perpendicular to the first direction. The measurement processor may be to determine, based upon a second set of scatterometry measurements, a second change in dimension of a second set of substrate features along the second direction, wherein the second set of substrate features is elongated along the first direction. The apparatus may include a control processor to generate an error signal when a figure of merit based upon the first change and the second change lies outside a target range.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: March 5, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Morgan D. Evans, Simon Ruffell, Tristan Y. Ma, Kevin Anglin
  • Publication number: 20190027367
    Abstract: Methods for processing of a workpiece are disclosed. The actual rate at which different portions of an ion beam can process a workpiece, referred to as the processing rate profile, is determined by measuring the amount of material removed from, or added to, a workpiece by the ion beam as a function of ion beam position. An initial thickness profile of a workpiece to be processed is determined. Based on the initial thickness profile, a target thickness profile, and the processing rate profile of the ion beam, a first set of processing parameters are determined. The workpiece is then processed using this first set of processing parameters. In some embodiments, an updated thickness profile is determined after the first process and a second set of processing parameters are determined. A second process is performed using the second set of processing parameters. Optimizations to improve throughput are also disclosed.
    Type: Application
    Filed: September 26, 2018
    Publication date: January 24, 2019
    Inventors: Morgan D. Evans, Kevin Anglin, Ross Bandy
  • Publication number: 20190027396
    Abstract: A method may include providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising an insulator layer and a silicon layer. The silicon layer may be disposed on the insulator layer, where the silicon layer comprises a first silicon thickness variation. The method may include forming an oxide layer on the silicon layer, where the oxide layer has a uniform thickness. The method may include selectively etching the oxide layer on the silicon layer, wherein the oxide layer comprises a first non-uniform oxide thickness. After thermal processing of the SOI substrate in an oxygen ambient, the non-uniform oxide thickness may be configured to generate a second silicon thickness variation in the silicon layer, less than the first silicon thickness variation.
    Type: Application
    Filed: October 9, 2017
    Publication date: January 24, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Andrew M. Waite, Morgan D. Evans, John Hautala
  • Publication number: 20180340769
    Abstract: An apparatus may include a processor and memory unit, including a control routine having a measurement processor to determine, based upon a first set of scatterometry measurements, a first change in a first dimension of a first set of substrate features along a first direction. The first set of substrate features may be elongated along a second direction perpendicular to the first direction. The measurement processor may be to determine, based upon a second set of scatterometry measurements, a second change in dimension of a second set of substrate features along the second direction, wherein the second set of substrate features is elongated along the first direction. The apparatus may include a control processor to generate an error signal when a figure of merit based upon the first change and the second change lies outside a target range.
    Type: Application
    Filed: May 25, 2017
    Publication date: November 29, 2018
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Morgan D. Evans, Simon Ruffell, Tristan Y. MA, Kevin Anglin
  • Patent number: 10090166
    Abstract: A method may include performing a chemical mechanical polishing (CMP) etch of a fin assembly disposed on a substrate, the fin assembly comprising a plurality of fin structures coated with an oxide layer, wherein as a result of the CMP etch, a first portion of the oxide layer is removed, and the fin structures remain covered with oxide. The method may further include performing a selective area processing (SAP) etch using ions, wherein a second portion of the oxide layer is removed in a non-uniform manner, wherein after the SAP etch, the fin structures remain covered with oxide.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: October 2, 2018
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Andrew Michael Waite, Morgan D. Evans, Johannes M. van Meer, Jae Young Lee
  • Patent number: 10081861
    Abstract: Methods for the selective processing of the outer portion of a workpiece are disclosed. The outer portion is processed by directing an ion beam toward the workpiece, where the ion beam extends beyond the outer edge of the workpiece at two locations. The workpiece is then rotated relative to the ion beam about the center so that all regions of the outer portion are exposed to the ion beam. The workpiece may be rotated an integral number of rotations. The ion beam may perform any process, such as ion implantation, etching or deposition. The outer portion may be an annular ring having an outer diameter equal to that of the workpiece and having a width of 1 to 30 millimeters. The rotation of the workpiece may be aligned with a notch on the outer edge of the workpiece.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: September 25, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Morgan D. Evans, Daniel Distaso, Stanislav S. Todorov, Mark R. Amato, William Davis Lee, Jillian Reno
  • Publication number: 20180197747
    Abstract: A method may include performing a chemical mechanical polishing (CMP) etch of a fin assembly disposed on a substrate, the fin assembly comprising a plurality of fin structures coated with an oxide layer, wherein as a result of the CMP etch, a first portion of the oxide layer is removed, and the fin structures remain covered with oxide. The method may further include performing a selective area processing (SAP) etch using ions, wherein a second portion of the oxide layer is removed in a non-uniform manner, wherein after the SAP etch, the fin structures remain covered with oxide.
    Type: Application
    Filed: January 6, 2017
    Publication date: July 12, 2018
    Inventors: Andrew Michael Waite, Morgan D. Evans, Johannes M. van Meer, Jae Young Lee
  • Publication number: 20180197796
    Abstract: An apparatus of a wafer processing apparatus includes at least one memory and logic, at least a portion of which is implemented in circuitry of the wafer processing apparatus including at least one processor coupled to the at least one memory. The logic may provide a 3D model of a surface of a wafer, the wafer defining a wafer plane; and modify a surface feature in a Z-direction along the surface of the wafer based on at least one of: an X-critical dimension (CD) extending along an X-direction of the wafer plane, and a Y-CD extending along a Y direction of the wafer plane.
    Type: Application
    Filed: January 6, 2017
    Publication date: July 12, 2018
    Inventors: Morgan D. Evans, Tristan Ma, Kevin Anglin, Motoya Okazaki, Johannes M. van Meer
  • Publication number: 20180174843
    Abstract: A method of etching a workpiece comprising two or more materials is disclosed. The method involves using physical sputtering as the etching method where the processing parameters of the sputtering process are tuned to achieve a desired etch rate selectivity. The method includes determining the etch rate of each material disposed on the workpiece as a function of various processing parameters, such as ion species, ion energy, incidence angle and temperature. Once the relationship between etch rate and these parameters is determined for each material, a set of values for these processing parameters may be chosen to achieve the desired etch rate selectivity.
    Type: Application
    Filed: December 16, 2016
    Publication date: June 21, 2018
    Inventors: Kevin Anglin, Tristan Ma, Morgan D. Evans, John Hautala, Heyun Yin
  • Patent number: 10002764
    Abstract: A method of etching a workpiece comprising two or more materials is disclosed. The method involves using physical sputtering as the etching method where the processing parameters of the sputtering process are tuned to achieve a desired etch rate selectivity. The method includes determining the etch rate of each material disposed on the workpiece as a function of various processing parameters, such as ion species, ion energy, incidence angle and temperature. Once the relationship between etch rate and these parameters is determined for each material, a set of values for these processing parameters may be chosen to achieve the desired etch rate selectivity.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: June 19, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Kevin Anglin, Tristan Ma, Morgan D. Evans, John Hautala, Heyun Yin
  • Patent number: 9933314
    Abstract: An improved system and method of measuring the temperature of a workpiece being processed is disclosed. The temperature measurement system determines a temperature of a workpiece by measuring the amount of expansion in the workpiece due to thermal expansion. The amount of expansion may be measured using a number of different techniques. In certain embodiments, a light source and a light sensor are disposed on opposite sides of the workpiece. The total intensity of the signal received by the light sensor may be indicative of the dimension of the workpiece. In another embodiment, an optical micrometer may be used. In another embodiment, a light sensor may be used in conjunction with a separate device that measures the position of the workpiece.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: April 3, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Klaus Petry, Jason M. Schaller, Ala Moradian, Morgan D. Evans
  • Patent number: 9899242
    Abstract: A system for heating substrates while being transported between processing chambers is disclosed. The system comprises an array of light emitting diodes (LEDs) disposed in the transfer chamber. The LEDs may be GaN LEDs, which emit light at a wavelength which is readily absorbed by silicon, thus efficiently and quickly heating the substrate. A controller is in communication with the LEDs. The LEDs may be independently controllable, so that the LEDs that are disposed above the substrate as it is moved from one processing chamber to another are illuminated. In other words, the illumination of the LEDs and the movements of the substrate handling robot may be synchronized by the controller.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: February 20, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Jason M. Schaller, Morgan D. Evans, Ala Moradian, Robert Brent Vopat, David Blahnik, William T. Weaver
  • Publication number: 20180003567
    Abstract: An improved system and method of measuring the temperature of a workpiece being processed is disclosed. The temperature measurement system determines a temperature of a workpiece by measuring the amount of expansion in the workpiece due to thermal expansion. The amount of expansion may be measured using a number of different techniques. In certain embodiments, a light source and a light sensor are disposed on opposite sides of the workpiece. The total intensity of the signal received by the light sensor may be indicative of the dimension of the workpiece. In another embodiment, an optical micrometer may be used. In another embodiment, a light sensor may be used in conjunction with a separate device that measures the position of the workpiece.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Klaus Petry, Jason M. Schaller, Ala Moradian, Morgan D. Evans