Patents by Inventor Morihisa Hirata
Morihisa Hirata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8749932Abstract: A protection circuit includes a first power supply system including a first power supply and a first ground, a second power supply system including a second power supply and a second ground, and a control circuit that, when coupled to an electro-static discharge (ESD) stress being applied to the first power supply system, controls a first switch. The first switch is provided between the signal line and the first ground. The control circuit includes a capacitance element, a resistance element in series with the capacitance element, and an inverter, an output of the inverter being connected between a gate of the first switch, an input of the inverter being connected to a connecting point between the capacitance element and the resistance element.Type: GrantFiled: August 15, 2012Date of Patent: June 10, 2014Assignee: Renesas Electronics CorporationInventors: Masanori Tanaka, Morihisa Hirata, Hitoshi Okamoto
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Publication number: 20120307408Abstract: A protection circuit includes a first power supply system including a first power supply and a first ground, a second power supply system including a second power supply and a second ground, and a control circuit that, when coupled to an electro-static discharge (ESD) stress being applied to the first power supply system, controls a first switch. The first switch is provided between the signal line and the first ground. The control circuit includes a capacitance element, a resistance element in series with the capacitance element, and an inverter, an output of the inverter being connected between a gate of the first switch, an input of the inverter being connected to a connecting point between the capacitance element and the resistance element.Type: ApplicationFiled: August 15, 2012Publication date: December 6, 2012Applicant: Renesas Electronics CorporationInventors: Masanori TANAKA, Morihisa Hirata, Hitoshi Okamoto
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Patent number: 8270132Abstract: A protection circuit that includes a first power supply system including a first power supply and a first ground, a second power supply system including a second power supply and a second ground, the second power supply system being connected to the first power supply system via a signal line through which signal transfer is performed between a circuit in the first power supply system and a circuit in the second power supply system, and a control circuit that, when coupled to an electro-static discharge (ESD) stress being applied to the first power supply system controls a switch, the switch being provided between the signal line and the first power supply.Type: GrantFiled: January 7, 2011Date of Patent: September 18, 2012Assignee: Renesas Electronics CorporationInventors: Masanori Tanaka, Morihisa Hirata, Hitoshi Okamoto
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Patent number: 8230373Abstract: An ESD analysis method and computer program product are disclosed. A circuit simulation is executed of design data of a semiconductor integrated circuit including a first power supply pad, a second power supply pad and a plurality of current paths between the first power supply pad and the second power supply pad, to calculate potentials in the plurality of current paths, when one of an ESD current and an ESD voltage is applied between the first power supply pad and the second power supply pad. An ESD tolerance is checked by calculating a potential difference between a first node coupled to the first power supply pad and a second node coupled to the second power supply pad, based on the calculated potentials. The first node and the second node are determined as nodes to be coupled to a border cell upon the potential difference being lower than a predetermined value.Type: GrantFiled: September 2, 2010Date of Patent: July 24, 2012Assignee: Renesas Electronics CorporationInventors: Susumu Kobayashi, Morihisa Hirata, Mototsugu Okushima, Tomohiro Kitayama, Tetsuya Katou
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Patent number: 8008727Abstract: To reduce the leak current in the MOSFET connected between the pad and the ground. There are provided a pad PAD for an input or output signal, an n-type MOSFET M1a connected between the pad PAD and the ground and having its gate terminal and backgate connected in common, and a potential control circuit 10 that controls a potential Vb of the gate terminal and the backgate of the n-type MOSFET M1a based on a potential Vin of the pad PAD. The potential control circuit 10 comprises n-type MOSFETs M2 and M3; the n-type MOSFET M1a has its gate terminal and backgate connected to backgates and drains of the n-type MOSFETs M2 and M3; the n-type MOSFET M2 has its source grounded and its gate terminal connected to the pad PAD via a resistance R; and the n-type MOSFET M3 has its source connected to the pad PAD and its gate terminal grounded.Type: GrantFiled: January 31, 2008Date of Patent: August 30, 2011Assignee: Renesas Electronics CorporationInventors: Hitoshi Okamoto, Morihisa Hirata
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Patent number: 7986156Abstract: An exemplary aspect of an embodiment of the present invention is a semiconductor device including a plurality of test elements formed in an array on a semiconductor substrate, an address signal generating portion that generates an address signal corresponding to each of the test elements, and a digital-to-analog converter that converts the address signal into an analog signal and outputs the converted analog signal. The present invention enables to recognize which DUT is being measured.Type: GrantFiled: February 27, 2009Date of Patent: July 26, 2011Assignee: Renesas Electronics CorporationInventors: Jun Ikeda, Morihisa Hirata
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Publication number: 20110102962Abstract: A protection circuit that includes a first power supply system including a first power supply and a first ground, a second power supply system including a second power supply and a second ground, the second power supply system being connected to the first power supply system via a signal line through which signal transfer is performed between a circuit in the first power supply system and a circuit in the second power supply system, and a control circuit that, when coupled to an electro-static discharge (ESD) stress being applied to the first power supply system controls a switch, the switch being provided between the signal line and the first power supply.Type: ApplicationFiled: January 7, 2011Publication date: May 5, 2011Applicant: Renesas Electronics CorporationInventors: Masanori Tanaka, Morihisa Hirata, Hitoshi Okamoto
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Publication number: 20110022376Abstract: An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate potentials in a plurality of current paths between pads of different two of the plurality of power supply systems, when one of an ESD current and an ESD voltage is applied between the pads. The border cell extraction unit extracts border cells from circuits of the different two of the plurality of power supply systems, wherein the circuits are included in the plurality of circuits, the border cells input and/or output signals between the circuits. The check unit checks an ESD tolerance by calculating a potential difference between the border cells, based on the calculated potentials, the extracted border cells.Type: ApplicationFiled: September 2, 2010Publication date: January 27, 2011Inventors: Susumu Kobayashi, Morihisa Hirata, Mototsugu Okushima, Tomohiro Kitayama, Tetsuya Katou
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Patent number: 7869174Abstract: Disclosed is a semiconductor integrated circuit device that includes an output circuit with power thereof supplied from one power supply system, an input circuit with an input terminal thereof connected to an output terminal of the output circuit through a signal line and with power thereof supplied from other power supply system different from the one power supply system, and a circuit that restrains a current flowing from the output circuit into the signal line when an ESD stress is applied from the output circuit to a signal transmitting/receiving portion of the input circuit.Type: GrantFiled: January 23, 2007Date of Patent: January 11, 2011Assignee: Renesas Electronics CorporationInventors: Masanori Tanaka, Morihisa Hirata, Hitoshi Okamoto
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Patent number: 7853909Abstract: An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate potentials in a plurality of current paths between pads of different two of the plurality of power supply systems, when one of an ESD current and an ESD voltage is applied between the pads. The border cell extraction unit extracts border cells from circuits of the different two of the plurality of power supply systems, wherein the circuits are included in the plurality of circuits, the border cells input and/or output signals between the circuits. The check unit checks an ESD tolerance by calculating a potential difference between the border cells, based on the calculated potentials, the extracted border cells.Type: GrantFiled: October 3, 2007Date of Patent: December 14, 2010Assignee: Renesas Electronics CorporationInventors: Susumu Kobayashi, Morihisa Hirata, Mototsugu Okushima, Tomohiro Kitayama, Tetsuya Katou
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Patent number: 7631279Abstract: A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unit to which electric power is supplied from first power supply wiring, and first ground wiring to which the first circuit unit is coupled. Moreover, the semiconductor integrated device includes a second circuit unit to which electric power is supplied from second power supply wiring, and second ground wiring coupled to the second circuit unit. The first circuit unit includes a first interface circuit unit, and the second circuit unit includes a second interface circuit unit configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring is coupled to the second ground wiring through a protection circuit, and the second interface circuit unit is placed in the vicinity of the first interface circuit unit.Type: GrantFiled: October 16, 2008Date of Patent: December 8, 2009Assignee: NEC Electronics CorporationInventor: Morihisa Hirata
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Patent number: 7624365Abstract: A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unit to which electric power is supplied from first power supply wiring, and first ground wiring to which the first circuit unit is coupled. Moreover, the semiconductor integrated device includes a second circuit unit to which electric power is supplied from second power supply wiring, and second ground wiring coupled to the second circuit unit. The first circuit unit includes a first interface circuit unit, and the second circuit unit includes a second interface circuit unit configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The second interface circuit unit is placed in the vicinity of the first interface circuit unit according to a determined arrangement.Type: GrantFiled: October 16, 2008Date of Patent: November 24, 2009Assignee: NEC Electronics CorporationInventor: Morihisa Hirata
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Publication number: 20090230987Abstract: An exemplary aspect of an embodiment of the present invention is a semiconductor device including a plurality of test elements formed in an array on a semiconductor substrate, an address signal generating portion that generates an address signal corresponding to each of the test elements, and a digital-to-analog converter that converts the address signal into an analog signal and outputs the converted analog signal. The present invention enables to recognize which DUT is being measured.Type: ApplicationFiled: February 27, 2009Publication date: September 17, 2009Applicant: NEC ELECTRONICS CORPORATIONInventors: Jun Ikeda, Morihisa Hirata
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Patent number: 7552404Abstract: A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unit to which electric power is supplied from first power supply wiring, and first ground wiring to which the first circuit unit is coupled. Moreover, the semiconductor integrated device includes a second circuit unit to which electric power is supplied from second power supply wiring, and second ground wiring coupled to the second circuit unit. The first circuit unit includes a first interface circuit unit, and the second circuit unit includes a second interface circuit unit configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring is coupled to the second ground wiring through a protection circuit, and the second interface circuit unit is placed in the vicinity of the first interface circuit unit.Type: GrantFiled: June 1, 2006Date of Patent: June 23, 2009Assignee: NEC Electronics CorporationInventor: Morihisa Hirata
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Publication number: 20090077516Abstract: A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unit 101 to which electric power is supplied from first power supply wiring 106, and first ground wiring 109 to which the first circuit unit is coupled. Moreover, the semiconductor integrated device includes a second circuit unit 102 to which electric power is supplied from second power supply wiring 113, and second ground wiring 116 coupled to the second circuit unit. The first circuit unit includes a first interface circuit unit 104, and the second circuit unit includes a second interface circuit unit 111 configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring is coupled to the second ground wiring through a protection circuit 117, and the second interface circuit unit is placed in the vicinity of the first interface circuit unit.Type: ApplicationFiled: October 16, 2008Publication date: March 19, 2009Inventor: Morihisa Hirata
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Publication number: 20090077517Abstract: A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unit 101 to which electric power is supplied from first power supply wiring 106, and first ground wiring 109 to which the first circuit unit is coupled. Moreover, the semiconductor integrated device includes a second circuit unit 102 to which electric power is supplied from second power supply wiring 113, and second ground wiring 116 coupled to the second circuit unit. The first circuit unit includes a first interface circuit unit 104, and the second circuit unit includes a second interface circuit unit 111 configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring is coupled to the second ground wiring through a protection circuit 117, and the second interface circuit unit is placed in the vicinity of the first interface circuit unit.Type: ApplicationFiled: October 16, 2008Publication date: March 19, 2009Inventor: Morihisa Hirata
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Publication number: 20080283986Abstract: A system-in-package type semiconductor device includes a plurality of semiconductor chips, a first semiconductor chip 1110 to which electric power is supplied from first power supply wiring 1111, and first ground wiring 1112 to which the first circuit unit is coupled. Moreover, the system-in-package type semiconductor device includes a second semiconductor chip 1120 to which electric power is supplied from second power supply wiring 1124, and second ground wiring 1125 coupled to the second circuit unit. The first semiconductor chip includes a first interface circuit unit 1412, and the second circuit unit includes a second interface circuit unit 1121 configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring 1414 is coupled to the second ground wiring 1424 through a protection circuit 1442, and the second interface circuit unit is placed in the vicinity of the first interface circuit unit.Type: ApplicationFiled: October 25, 2007Publication date: November 20, 2008Inventor: Morihisa Hirata
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Publication number: 20080185653Abstract: To reduce the leak current in the MOSFET connected between the pad and the ground. There are provided a pad PAD for an input or output signal, an n-type MOSFET M1a connected between the pad PAD and the ground and having its gate terminal and backgate connected in common, and a potential control circuit 10 that controls a potential Vb of the gate terminal and the backgate of the n-type MOSFET M1a based on a potential Vin of the pad PAD. The potential control circuit 10 comprises n-type MOSFETs M2 and M3; the n-type MOSFET M1a has its gate terminal and backgate connected to backgates and drains of the n-type MOSFETs M2 and M3; the n-type MOSFET M2 has its source grounded and its gate terminal connected to the pad PAD via a resistance R; and the n-type MOSFET M3 has its source connected to the pad PAD and its gate terminal grounded.Type: ApplicationFiled: January 31, 2008Publication date: August 7, 2008Applicant: NEC ELECTRONICS CORPORATIONInventors: Hitoshi Okamoto, Morihisa Hirata
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Publication number: 20080104554Abstract: An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate potentials in a plurality of current paths between pads of different two of the plurality of power supply systems, when one of an ESD current and an ESD voltage is applied between the pads. The border cell extraction unit extracts border cells from circuits of the different two of the plurality of power supply systems, wherein the circuits are included in the plurality of circuits, the border cells input and/or output signals between the circuits. The check unit checks an ESD tolerance by calculating a potential difference between the border cells, based on the calculated potentials, the extracted border cells.Type: ApplicationFiled: October 3, 2007Publication date: May 1, 2008Inventors: Susumu Kobayashi, Morihisa Hirata, Mototsugu Okushima, Tomohiro Kitayama, Tetsuya Katou
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Patent number: 7312517Abstract: A system-in-package type semiconductor device includes a plurality of semiconductor chips, a first semiconductor chip 1110 to which electric power is supplied from first power supply wiring 1111, and first ground wiring 1112 to which the first circuit unit is coupled. Moreover, the system-in-package type semiconductor device includes a second semiconductor chip 1120 to which electric power is supplied from second power supply wiring 1124, and second ground wiring 1125 coupled to the second circuit unit. The first semiconductor chip includes a first interface circuit unit 1412, and the second circuit unit includes a second interface circuit unit 1121 configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring 1414 is coupled to the second ground wiring 1424 through a protection circuit 1442, and the second interface circuit unit is placed in the vicinity of the first interface circuit unit.Type: GrantFiled: October 6, 2005Date of Patent: December 25, 2007Assignee: NEC Electronics CorporationInventor: Morihisa Hirata