Abstract: Disclosed is a semiconductor integrated circuit device that includes an output circuit with power thereof supplied from one power supply system, an input circuit with an input terminal thereof connected to an output terminal of the output circuit through a signal line and with power thereof supplied from other power supply system different from the one power supply system, and a circuit that restrains a current flowing from the output circuit into the signal line when an ESD stress is applied from the output circuit to a signal transmitting/receiving portion of the input circuit.

Abstract: In a semiconductor device having an electrostatic discharge protection arrangement, a semiconductor substrate exhibits a first conductivity type. First and second impurity regions each exhibiting a second conductivity type are formed in the semiconductor substrate. A channel region is formed in the semiconductor substrate between the first and second impurity regions. A first conductive area is defined on the first impurity region in the vicinity of the channel region. A second conductive area is defined on the first impurity region so as to be supplied with an electrostatic discharge current. A third conductive area is defined on the first impurity region to establish an electrical connection between the first and second conductive area. At least one heat-radiation area is defined in the third conductive area so as to be at least partially isolated therefrom and thermally contacted with the first conductive area.

Abstract: A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unit 101 to which electric power is supplied from first power supply wiring 106, and first ground wiring 109 to which the first circuit unit is coupled. Moreover, the semiconductor integrated device includes a second circuit unit 102 to which electric power is supplied from second power supply wiring 113, and second ground wiring 116 coupled to the second circuit unit. The first circuit unit includes a first interface circuit unit 104, and the second circuit unit includes a second interface circuit unit 111 configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring is coupled to the second ground wiring through a protection circuit 117, and the second interface circuit unit is placed in the vicinity of the first interface circuit unit.

Abstract: A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unit 101 to which electric power is supplied from first power supply wiring 106, and first ground wiring 109 to which the first circuit unit is coupled. Moreover, the semiconductor integrated device includes a second circuit unit 102 to which electric power is supplied from second power supply wiring 113, and second ground wiring 116 coupled to the second circuit unit. The first circuit unit includes a first interface circuit unit 104, and the second circuit unit includes a second interface circuit unit 111 configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring is coupled to the second ground wiring through a protection circuit 117, and the second interface circuit unit is placed in the vicinity of the first interface circuit unit.

Abstract: A system-in-package type semiconductor device includes a plurality of semiconductor chips, a first semiconductor chip 1110 to which electric power is supplied from first power supply wiring 1111, and first ground wiring 1112 to which the first circuit unit is coupled. Moreover, the system-in-package type semiconductor device includes a second semiconductor chip 1120 to which electric power is supplied from second power supply wiring 1124, and second ground wiring 1125 coupled to the second circuit unit. The first semiconductor chip includes a first interface circuit unit 1412, and the second circuit unit includes a second interface circuit unit 1121 configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring 1414 is coupled to the second ground wiring 1424 through a protection circuit 1442, and the second interface circuit unit is placed in the vicinity of the first interface circuit unit.

Abstract: To calculate pin-to-pin delay time, which is delay time from the input pin to the output pin of a logic block, and block-to-block delay time, which is delay time from an output pin of one block to an input pin of the next block, firstly, the pin-to-pin delay time and the block-to-block delay time are calculated with negligence in aging caused by a hot carrier effect, secondly, degradations caused by aged transistors connected to the input pin and the output pin, and lastly, the pin-to-pin delay time and block-to-block delay time are modified by the degradation rate.

Abstract: In a semiconductor device having an electrostatic discharge protection arrangement, a semiconductor substrate exhibits a first conductivity type. First and second impurity regions each exhibiting a second conductivity type are formed in the semiconductor substrate. A channel region is formed in the semiconductor substrate between the first and second impurity regions. A first conductive area is defined on the first impurity region in the vicinity of the channel region. A second conductive area is defined on the first impurity region so as to be supplied with an electrostatic discharge current. A third conductive area is defined on the first impurity region to establish an electrical connection between the first and second conductive area. At least one heat-radiation area is defined in the third conductive area so as to be at least partially isolated therefrom and thermally contacted with the first conductive area.

Abstract: A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unit 101 to which electric power is supplied from first power supply wiring 106, and first ground wiring 109 to which the first circuit unit is coupled. Moreover, the semiconductor integrated device includes a second circuit unit 102 to which electric power is supplied from second power supply wiring 113, and second ground wiring 116 coupled to the second circuit unit.

Abstract: A protective circuit includes a floating gate MOSFET having a source-drain path connected between an I/O line and a source line or a ground line, a control gate connected to the I/O line and a floating gate connected to the source line or the ground line.

Abstract: A design automation method is provided which reduces complication of design work resulting from individual verification of a plurality of objects to be verified, for example, electromigration and hot carrier effect. Limiting values are prepared individually for the objects to be verified while a combined limiting value is obtained by combining these limiting values. By the use of the combined limiting value, verification of reliability is performed for all the objects. Specifically, when applied to the electromigration and the hot carrier effect as the objects to be verified, verification can simultaneously be performed upon frequency limiting values for the electromigration and the hot carrier effect.

Abstract: To calculate pin-to-pin delay time, which is delay time from the input pin to the output pin of a logic block, and block-to-block delay time, which is delay time from an output pin of one block to an input pin of the next block, firstly, the pin-to-pin delay time and the block-to-block delay time are calculated with negligence in aging caused by a hot carrier effect, secondly, degradations caused by aged transistors connected to the input pin and the output pin, and lastly, the pin-to-pin delay time and block-to-block delay time are modified by the degradation rate.

Abstract: A semiconductor device is provided, which is provided with a high resistance to surge currents. The semiconductor device comprises three N+ diffusion layers 4a, 4b, and 4c in a region surrounded by an element-separating insulating film 3a. The N+ diffusion layer 4a forms a source diffusion layer of an N-channel MOS transistor 11a, the N+ diffusion layer 4c forms a source diffusion layer of another N-channel MOS transistor 11b, and the N+ diffusion layer 4b forms drain diffusion layers for two N-channel MOS transistors 11a and 11b. That is, respective drain diffusion layers of two N-channel MOS transistors are shared. Furthermore, a ring-shaped mask insulating film 18 is formed on the N+ diffusion layer 4b. A silicide layer 6b is formed on the N+ diffusion layer 4b except the area covered by the ring-shaped mask insulating film 18.

Abstract: A protective circuit includes a floating gate MOSFET having a source-drain path connected between an I/O line and a source line or a ground line, a control gate connected to the I/O line and a floating gate connected to the source line or the ground line.

Abstract: A semiconductor device includes a protective circuit at an input/output port thereof, wherein the protective circuit includes a plurality of protective MOS transistors. A diffused region is disposed between the n-type source/drain regions and a guard ring formed in a p-well for encircling the source/drain regions of the protective transistors. The diffused region is of lightly doped p-type or of an n-type and increases the resistance of a parasitic bipolar transistor formed in association with the protective transistors. The increase of the resistance assists protective function of the protective device against an ESD failure of the internal circuit of the semiconductor device.

Abstract: A semiconductor device includes a protective circuit at an input/output port thereof, wherein the protective circuit includes a plurality of protective MOS transistors. A diffused region is disposed between the n-type source/drain regions and a guard ring formed in a p-well for encircling the source/drain regions of the protective transistors. The diffused region is of lightly doped p-type or of an n-type and increases the resistance of a parasitic bipolar transistor formed in association with the protective transistors. The increase of the resistance assists protective function of the protective device against an ESD failure of the internal circuit of the semiconductor device.

Abstract: In a method for designing an integrated circuit device, maximum load capacities of a number of circuit elements are calculated by a simulation method. The maximum load capacities are stored in a database, or approximation formulae are calculated therefrom. A maximum load capacity for a circuit element is retrieved from the database or is approximately calculated by using a corresponding one of the approximation formulae in accordance with input conditional data. Then, the integrated circuit device is designed so as to make a load capacity of each of circuit elements smaller than the retrieved or approximately calculated maximum load capacity.

Abstract: A semiconductor device includes a transistor and a protective resistance element. The transistor has first and second impurity regions of a first conductivity type formed on a surface of a substrate and serving as a source and a drain, respectively, and a gate electrode formed on a channel region sandwiched between the first and second impurity regions through a gate insulating film. The protective resistance element has a third impurity region of the first conductivity type formed on the surface of the substrate to be separated from the second impurity region by a predetermined distance, a control electrode formed on the substrate through an insulating film in a surface region sandwiched between the second and third impurity regions, and a well of the first conductivity type formed on the surface of the substrate in the surface region sandwiched between the second and third impurity regions to come into contact with them.

Abstract: The object of the present invention is to provide a semiconductor device, which has a high protective capability against an excessive voltage applied from the outside. The device is provided, in its analog switch 30, with a P type dummy transistor 11 whose drain terminal is connected to a P type diffusion layer in the outside of a P type transfer gate 4 and whose gate and source terminals are connected to a power supply potential, and an N type dummy transistor 12 whose drain terminal is connected to an N type diffusion layer in the outside of an N type transfer gate 5 and whose gate and source terminals are connected to a ground potential, and when an excessive voltage is applied from the outside, an excessive current is made to flow through the P type and N type dummy transistors 11 and 12 to the power supply potential or the ground potential.

Abstract: A protective device for protecting a CMOS circuit included in an internal circuit of an IC against overvoltage applied to a power source wiring and preventing the CMOS from being latched-up by surge voltage due to external noise during a normal operation of the IC is disclosed. An N channel MOS FET and a P channel MOS FET are arranged in parallel to each other and connected between a power source wiring and a ground wiring. Gate electrodes of the N channel and the P channel MOS FETs are connected to the ground wiring and the power source wiring, respectively. Positive overvoltage or surge voltage applied to the power source wiring is relieved by breakdown of drain junctions of both the MOS FETs.