Patents by Inventor Moritz Andreas Meyer

Moritz Andreas Meyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9898572
    Abstract: A method of Back-End-Of-Line processing of a semiconductor device is provided including providing a layout for metal lines of a metallization layer of the semiconductor device, determining a semi-isolated metal line in the provided layout and shifting at least a portion of the determined semi-isolated metal line.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: February 20, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thomas Melde, Matthias U. Lehr, Thomas Herrmann, Jens Hassmann, Moritz Andreas Meyer, Rakesh Kumar Kuncha
  • Publication number: 20170235867
    Abstract: A method of Back-End-Of-Line processing of a semiconductor device is provided including providing a layout for metal lines of a metallization layer of the semiconductor device, determining a semi-isolated metal line in the provided layout and shifting at least a portion of the determined semi-isolated metal line.
    Type: Application
    Filed: February 17, 2016
    Publication date: August 17, 2017
    Inventors: Thomas Melde, Matthias U. Lehr, Thomas Herrmann, Jens Hassmann, Moritz Andreas Meyer, Rakesh Kumar Kuncha
  • Patent number: 9281252
    Abstract: A method includes providing a semiconductor structure. An external mechanical stress is applied to the semiconductor structure. One or more semiconductor manufacturing processes are performed while the external mechanical stress is applied to the semiconductor structure. The one or more semiconductor manufacturing processes provide one or more material layers having an intrinsic stress at the semiconductor structure. After performing the one or more semiconductor manufacturing processes, the external mechanical stress is removed from the semiconductor structure. The removal of the external mechanical stress at least partially relaxes the intrinsic stress of the one or more material layers.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: March 8, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Alexander Würfel, Moritz Andreas Meyer
  • Patent number: 8575029
    Abstract: By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: November 5, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Moritz Andreas Meyer, Matthias Lehr, Eckhard Langer
  • Publication number: 20120088365
    Abstract: By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced.
    Type: Application
    Filed: October 13, 2011
    Publication date: April 12, 2012
    Inventors: Moritz Andreas Meyer, Matthias Lehr, Eckhard Langer
  • Patent number: 8058731
    Abstract: By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: November 15, 2011
    Assignee: Advanced Micro Devices, Inc
    Inventors: Moritz Andreas Meyer, Matthias Lehr, Eckhard Langer
  • Patent number: 8058081
    Abstract: A method comprises providing a semiconductor structure. The semiconductor structure comprises a feature comprising a first material and a layer of a second material formed over the feature. The semiconductor structure is exposed to an etchant. The etchant is adapted to selectively remove the first material, leaving the second material substantially intact. After exposing the semiconductor structure to the etchant, it is detected whether the feature has been affected by the etchant.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: November 15, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Moritz Andreas Meyer, Eckhard Langer, Frank Koschinsky
  • Publication number: 20080268265
    Abstract: By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced.
    Type: Application
    Filed: December 7, 2007
    Publication date: October 30, 2008
    Inventors: Moritz Andreas Meyer, Matthias Lehr, Eckhard Langer
  • Publication number: 20080160654
    Abstract: A method comprises providing a semiconductor structure. The semiconductor structure comprises a feature comprising a first material and a layer of a second material formed over the feature. The semiconductor structure is exposed to an etchant. The etchant is adapted to selectively remove the first material, leaving the second material substantially intact. After exposing the semiconductor structure to the etchant, it is detected whether the feature has been affected by the etchant.
    Type: Application
    Filed: July 13, 2007
    Publication date: July 3, 2008
    Inventors: Moritz Andreas Meyer, Eckhard Langer, Frank Koschinsky
  • Patent number: 6953755
    Abstract: By preparing fully-embedded interconnect structure samples for a cross-section analysis by means of electron microscopy or x-ray microscopy, degradation mechanisms may be efficiently monitored. Moreover, displaying some of the measurement results as a quick motion representation enables the detection of subtle changes of characteristics of an interconnect structure in a highly efficient manner.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: October 11, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Moritz Andreas Meyer, Ehrenfried Zschech, Eckhard Langer