Patents by Inventor Morteza Afghahi
Morteza Afghahi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6555805Abstract: Briefly, in one embodiment, the present invention provides a circuit for offset reduction in an active pixel sensor array. The circuit includes a voltage regulator to regulate or reset voltage at an output port of the voltage regulator for a pixel of the active pixel sensor array. The circuit further includes at least one programmable device coupled to the regulator, to adjust the reset voltage to reduce the offset by a first value.Type: GrantFiled: November 20, 2001Date of Patent: April 29, 2003Assignee: Intel CorporationInventor: Morteza Afghahi
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Patent number: 6525769Abstract: An imaging device includes a compensation circuit for reducing an effect of dark current generated during operation. The compensation circuit calculates an initial dark current offset value using optically dark regions of a photo sensitive array. The compensation circuit also automatically adjusts the initial dark current offset value as output signals from successive rows of the photo sensitive array are transferred. The compensation circuit can calculate the initial dark current offset value each time an image is captured, thereby compensating for variables such as temperature.Type: GrantFiled: December 30, 1998Date of Patent: February 25, 2003Assignee: Intel CorporationInventors: Brent D. Thomas, Morteza Afghahi
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Patent number: 6486913Abstract: An image sensor circuit including a set of pixels associated with a pixel output node and a reset circuit associated with the set of pixels to set each pixel to a predetermined value.Type: GrantFiled: September 30, 1999Date of Patent: November 26, 2002Assignee: Intel CorporationInventors: Morteza Afghahi, Ramin Rajabian
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Patent number: 6414292Abstract: An image sensor is disclosed that provides improved image resolution, for a given integrated circuit die size, by eliminating one or more dedicated power supply lines that feed each sensor element of the sensor array, thereby allowing greater sensor element density. Each sensor element has a first switch that is coupled to a photodetector to alternatively, under the control of a reset signal, (1) provide a first current to reset the photodetector and (2) present high impedance to the photodetector. A reset line is coupled to the first switch in each of the sensor elements to provide the reset signal and to both control the first switch and supply the first current. Such an image sensor may be particularly desirable when built using a metal oxide semiconductor (MOS) fabrication process. The image sensor may be used in a variety of imaging systems, including digital cameras.Type: GrantFiled: October 29, 1999Date of Patent: July 2, 2002Assignee: Intel CorporationInventor: Morteza Afghahi
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Patent number: 6384394Abstract: Briefly, in one embodiment, the present invention provides a circuit for offset reduction in an active pixel sensor array. The circuit includes a voltage regulator to regulate or reset voltage at an output port of the voltage regulator for a pixel of the active pixel sensor array. The circuit further includes at least one programmable device coupled to the regulator, to adjust the reset voltage to reduce the offset by a first value.Type: GrantFiled: August 16, 1999Date of Patent: May 7, 2002Assignee: Intel CorporationInventor: Morteza Afghahi
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Patent number: 6380530Abstract: A method of operating a high sensitivity active pixel for use in metal oxide semiconductor (MOS) image sensor circuits. Light is allowed to be incident upon a photodetector circuit to thereby generate an input signal that represents the light. The input signal is applied to a gate of a first field effect transistor (FET). A control signal is applied to a drain of the FET and thereby generates an output current at a source of the FET. Charge is accumulated in a capacitor that is coupled to the source of the FET, where a voltage across the capacitor represents the detected incident light.Type: GrantFiled: February 8, 2000Date of Patent: April 30, 2002Assignee: Intel CorporationInventor: Morteza Afghahi
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Patent number: 6366320Abstract: A semiconductor circuit having an analog storage array, a sense amplifier array in which each sense amp cell generates a differential signal pair in response to receiving first and second signals from the storage array. The circuit also includes an analog multiplexer through which a selected differential signal pair is driven into a signal processing pipe. In another embodiment, the sense amp cells each include an operational amplifier (opamp) pair configured as unity-gain closed loop amplifiers for driving the differential signal pair through the analog multiplexer. To improve settling time, the opamps are designed to provide an underdamped response while loaded with the analog transmission path through the analog mux. In yet another embodiment, each sense amp cell is activated one clock cycle before it is read. This allows speedy readout while transitioning from one cell to the next.Type: GrantFiled: December 8, 1997Date of Patent: April 2, 2002Assignee: Intel CorporationInventors: Rajendran Nair, Mark A. Beiley, Morteza Afghahi
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Patent number: 6362666Abstract: An embodiment of the invention is directed to a buffer circuit having a closed loop negative feedback amplifier that is coupled to continuously drive a node to a predetermined set voltage. A precharge circuit is coupled to selectively drive the node at a higher rate than the amplifier. The buffer circuit is particularly useful for reducing the recovery and settling time of the node voltage when the node is suddenly subjected to a large, capacitive load.Type: GrantFiled: December 30, 1999Date of Patent: March 26, 2002Assignee: Intel CorporationInventors: Morteza Afghahi, Yueming He
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Publication number: 20020030152Abstract: Briefly, in one embodiment, the present invention provides a circuit for offset reduction in an active pixel sensor array. The circuit includes a voltage regulator to regulate or reset voltage at an output port of the voltage regulator for a pixel of the active pixel sensor array. The circuit further includes at least one programmable device coupled to the regulator, to adjust the reset voltage to reduce the offset by a first value.Type: ApplicationFiled: November 20, 2001Publication date: March 14, 2002Inventor: Morteza Afghahi
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Patent number: 6313455Abstract: The present invention includes, in one embodiment thereof, a pixel cell cell. The pixel cell includes a photosensor to detect light and a source following device. The source following device is coupled to the photosensor. The source following device has a source coupled to a select line that when asserted, permits reading out of information indicative of an intensity of light detected by the photosensor.Type: GrantFiled: August 16, 1999Date of Patent: November 6, 2001Assignee: Intel CorporationInventor: Morteza Afghahi
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Patent number: 6288666Abstract: An embodiment of the invention is directed to a metal oxide semiconductor field effect transistor (MOSFET) comparator, which includes a differential amplifier having first and second inputs and first and second outputs. A first offset storage device is connected to the first input at one end and receives a first input signal of the comparator at another end. A second offset storage device is connected to the second input at one end and receives the first input signal during an autozero time interval and a second input signal of the comparator thereafter. During the autozero time interval, offset voltages are stored. Thereafter, the offsets are cancelled when the input signals are applied to their respective storage device. In a particular embodiment of the invention, the amplifier features a dual purpose load that causes the amplifier to first preamplify and then regeneratively drives the outputs.Type: GrantFiled: November 8, 1999Date of Patent: September 11, 2001Assignee: Intel CorporationInventors: Morteza Afghahi, Yueming He
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Patent number: 6232757Abstract: An embodiment of the invention is directed to a voltage regulator that provides a conditioned reference voltage with high supply noise rejection. A reference circuit provides an input reference voltage. An operational amplifier (opamp) has a first opamp input coupled to the reference circuit, a second opamp input, and an opamp output to provide the conditioned reference voltage based on the input reference voltage. A differential MOS amplifier has a first input coupled to the opamp output and an output coupled to the second opamp input. The reference voltage is conditioned in accordance with the size of transistors in the differential amplifier. The voltage regulator may be used in different types of analog-to-digital converters, including those built for use with camera chips.Type: GrantFiled: August 10, 2000Date of Patent: May 15, 2001Assignee: Intel CorporationInventors: Morteza Afghahi, Yueming He
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Patent number: 6204795Abstract: A method is provided having the steps of receiving a first pixel signal; generating a first set of bits representative of the first pixel signal; receiving a second pixel signal; and, generating a second set of bits representative of a difference between the first pixel signal and the second pixel signal. An apparatus and system for performing the above method is also provided.Type: GrantFiled: January 8, 1999Date of Patent: March 20, 2001Assignee: Intel CorporationInventor: Morteza Afghahi
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Patent number: 6191412Abstract: Gain and error correction circuitry for metal-oxide-semiconductor (MOS) analog storage circuits, including image sensors. The correction circuitry allows the analog output signal for a storage cell to substantially track an input signal in each cell. Voltage dependent distortion and attenuation in the output signal, with respect to the input signal, is minimized, without significantly increasing the size of each cell.Type: GrantFiled: May 3, 2000Date of Patent: February 20, 2001Assignee: Intel CorporationInventor: Morteza Afghahi
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Patent number: 6144195Abstract: An embodiment of the invention is directed to a voltage regulator that provides a conditioned reference voltage with high supply noise rejection. A reference circuit provides an input reference voltage. An operational amplifier (opamp) has a first opamp input coupled to the reference circuit, a second opamp input, and an opamp output to provide the conditioned reference voltage based on the input reference voltage. A differential MOS amplifier has a first input coupled to the opamp output and an output coupled to the second opamp input. The reference voltage is conditioned in accordance with the size of transistors in the differential amplifier. The voltage regulator may be used in different types of analog-to-digital converters, including those built for use with camera chips.Type: GrantFiled: August 20, 1999Date of Patent: November 7, 2000Assignee: Intel CorporationInventors: Morteza Afghahi, Yueming He
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Patent number: 6124754Abstract: A reference circuit includes a first resistive element and a current source. The first resistive element is adapted to produce an output voltage based on a first current and a resistance of the first resistive element. The resistance of the first resistive element is a function of a temperature of the current. The current source includes a second resistive element that has a resistance that is a function of the temperature. The current source is adapted to adjust the first current to minimize variation of the output voltage with the temperature based on the resistance of the second resistive element.Type: GrantFiled: April 30, 1999Date of Patent: September 26, 2000Assignee: Intel CorporationInventor: Morteza Afghahi
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Patent number: 6111242Abstract: Imaging system with gain and error correction circuitry particularly suitable for metal-oxide-semiconductor (MOS) image sensors. The correction circuitry allows the analog output signal for an active pixel to substantially track an input signal in the pixel. Voltage dependent distortion and attenuation in the output signal, with respect to the input signal, is minimized, without significantly increasing the size of each pixel.Type: GrantFiled: January 2, 1998Date of Patent: August 29, 2000Assignee: Intel CorporationInventor: Morteza Afghahi
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Patent number: 6093924Abstract: Gain and error correction circuitry for metal-oxide-semiconductor (MOS) analog storage circuits, including image sensors. The correction circuitry allows the analog output signal for a storage cell to substantially track an input signal in each cell. Voltage dependent distortion and attenuation in the output signal, with respect to the input signal, is minimized, without significantly increasing the size of each cell.Type: GrantFiled: January 9, 1998Date of Patent: July 25, 2000Assignee: Intel CorporationInventor: Morteza Afghahi
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Patent number: 6046444Abstract: A high sensitivity active pixel for use in MOS image sensor circuits. The pixel circuit design allows the use of digital MOS fabrication processes to be used in implementing a pixel circuit having greater sensitivity (allowing increased frame rate) and greater noise immunity than certain prior art pixels. The novel pixel features a source follower configured amplifier, such as a single MOS FET, coupled between a photodetector and a storage capacitor. A light-generated signal from the photodetector is used to control the charge placed in the storage capacitor in order to develop a capture voltage. In a particular embodiment, an n-channel source follower and a p-channel output stage are combined in the pixel to make the overall transfer function of the pixel more linear and distortion-free.Type: GrantFiled: December 8, 1997Date of Patent: April 4, 2000Assignee: Intel CorporationInventor: Morteza Afghahi
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Patent number: 5955899Abstract: A compact electronic comparator circuit is featuring a single amplifier having two loads. The comparator is a symmetrical circuit having a pair of transistors to which positive and negative feedback loads are coupled so as to yield a constant infinite load. The comparator first amplifies the two input signals, and then operates as a regenerative latch in response to an external signal once the input signals have been sufficiently amplified. The comparator may be used in A/D converter and DRAM applications.Type: GrantFiled: January 27, 1997Date of Patent: September 21, 1999Assignee: Intel CorporationInventor: Morteza Afghahi