Patents by Inventor Moses Ho
Moses Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10686035Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.Type: GrantFiled: October 9, 2018Date of Patent: June 16, 2020Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
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Publication number: 20190115427Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.Type: ApplicationFiled: October 9, 2018Publication date: April 18, 2019Inventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
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Patent number: 10121857Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.Type: GrantFiled: May 1, 2015Date of Patent: November 6, 2018Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
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Publication number: 20180240872Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.Type: ApplicationFiled: May 1, 2015Publication date: August 23, 2018Inventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
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Patent number: 9647059Abstract: This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types.Type: GrantFiled: June 8, 2014Date of Patent: May 9, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Lingping Guan, Madhur Bobde, Anup Bhalla, Yeeheng Lee, John Chen, Moses Ho
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Publication number: 20170125514Abstract: This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a . drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types.Type: ApplicationFiled: June 8, 2014Publication date: May 4, 2017Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Yeeheng Lee, John Chen, Moses Ho
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Publication number: 20160322459Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.Type: ApplicationFiled: May 1, 2015Publication date: November 3, 2016Inventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
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Publication number: 20150357406Abstract: This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a . drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types.Type: ApplicationFiled: June 8, 2014Publication date: December 10, 2015Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Yeeheng Lee, John Chen, Moses Ho
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Patent number: 9093521Abstract: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.Type: GrantFiled: June 24, 2013Date of Patent: July 28, 2015Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Anup Bhalla, Xiaobin Wang, Moses Ho
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Patent number: 9024375Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.Type: GrantFiled: August 26, 2012Date of Patent: May 5, 2015Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hamza Yilmaz, Daniel Ng, Lingpeng Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
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Patent number: 8969953Abstract: Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate Source and body regions are formed by implanting dopants onto the filled trenches. This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns.Type: GrantFiled: August 26, 2013Date of Patent: March 3, 2015Assignee: Alpha and Omega Semiconductor IncorporatedInventors: John Chen, Yeeheng Lee, Lingpeng Guan, Moses Ho, Wilson Ma, Anup Bhalla, Hamza Yilmaz
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Publication number: 20140374823Abstract: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.Type: ApplicationFiled: June 24, 2013Publication date: December 25, 2014Inventors: Anup Bhalla, Xiaobin Wang, Moses Ho
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Patent number: 8785306Abstract: A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.Type: GrantFiled: September 27, 2011Date of Patent: July 22, 2014Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Yeeheng Lee, John Chen, Moses Ho
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Publication number: 20130341689Abstract: Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate Source and body regions are formed by implanting dopants onto the filled trenches. This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns.Type: ApplicationFiled: August 26, 2013Publication date: December 26, 2013Applicant: Alpha & Omega Semiconductor IncorporatedInventors: John Chen, Yeeheng Lee, Lingpeng Guan, Moses Ho, Wilson Ma, Anup Bhalla, Hamza Yilmaz
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Publication number: 20130221430Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.Type: ApplicationFiled: August 26, 2012Publication date: August 29, 2013Inventors: Hamza Yilmaz, Daniel Ng, Lingpeng Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
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Patent number: 8519476Abstract: Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns.Type: GrantFiled: December 21, 2009Date of Patent: August 27, 2013Assignee: Alpha and Omega Semiconductor IncorporatedInventors: John Chen, Yeeheng Lee, Lingpeng Guan, Moses Ho, Wilson Ma, Anup Bhalla, Hamza Yilmaz
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Patent number: 8471332Abstract: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.Type: GrantFiled: January 12, 2012Date of Patent: June 25, 2013Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Anup Bhalla, Xiaobin Wang, Moses Ho
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Publication number: 20130075855Abstract: A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.Type: ApplicationFiled: September 27, 2011Publication date: March 28, 2013Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Yeeheng Lee, John Chen, Moses Ho
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Publication number: 20130009238Abstract: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.Type: ApplicationFiled: January 12, 2012Publication date: January 10, 2013Inventors: Anup Bhalla, Xiaobin Wang, Moses Ho
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Patent number: 8263482Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.Type: GrantFiled: March 31, 2011Date of Patent: September 11, 2012Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hamza Yilmaz, Daniel Ng, Lingpeng Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen