Patents by Inventor Moses Ho
Moses Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8105895Abstract: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.Type: GrantFiled: February 17, 2011Date of Patent: January 31, 2012Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Anup Bhalla, Xiaobin Wang, Moses Ho
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Patent number: 8008151Abstract: A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.Type: GrantFiled: November 9, 2007Date of Patent: August 30, 2011Assignee: Alpha and Omega Semiconductor LimitedInventors: Sung-Shan Tai, Tiesheng Li, Anup Bhalla, Hong Chang, Moses Ho
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Publication number: 20110183499Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.Type: ApplicationFiled: March 31, 2011Publication date: July 28, 2011Inventors: Hamza Yilmaz, Daniel Ng, Lingpeng Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
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Publication number: 20110147830Abstract: Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns.Type: ApplicationFiled: December 21, 2009Publication date: June 23, 2011Applicant: Alpha and Omega Semiconductor IncorporatedInventors: John Chen, Yeeheng Lee, Lingpeng Guan, Moses Ho, Wilson Ma, Anup Bhalla, Hamza Yilmaz
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Publication number: 20110140194Abstract: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.Type: ApplicationFiled: February 17, 2011Publication date: June 16, 2011Inventors: Anup Bhalla, Xiaobin Wang, Moses Ho
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Patent number: 7952139Abstract: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.Type: GrantFiled: June 30, 2008Date of Patent: May 31, 2011Assignee: Alpha & Omega Semiconductor Ltd.Inventors: Anup Bhalla, Xiaobin Wang, Moses Ho
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Patent number: 7943989Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.Type: GrantFiled: December 31, 2008Date of Patent: May 17, 2011Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hamza Yilmaz, Daniel Ng, Lingpeng Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
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Patent number: 7892924Abstract: A method is disclosed for making a substantially charge balanced multi-nano shell drift region (MNSDR) for superjunction semiconductor devices atop a base substrate. The MNSDR has numerous concentric nano shell members NSM1, NSM2, . . . , NSMM (M>1) of alternating, substantially charge balanced first conductivity type and second conductivity type and with height NSHT. First, a bulk drift layer (BDL) is formed atop the base substrate. A substantially vertical cavity of pre-determined shape and size and with depth NSHT is then created into the top surface of BDL. The shell members NSM1, NSM2, . . . , NSMM are successively formed inside the vertical cavity, initially upon its vertical walls then moving toward its center, so as to successively fill the vertical cavity till a residual space remains therein. A semi-insulating or insulating fill-up nano plate is then formed inside the residual space to fill it up.Type: GrantFiled: December 2, 2009Date of Patent: February 22, 2011Assignee: Alpha and Omega Semiconductor, Inc.Inventors: Yeeheng Lee, Moses Ho, Lingpeng Guan
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Patent number: 7875541Abstract: Fabricating a semiconductor device includes forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate having a gate top surface that extends substantially above the top substrate surface at least in center region of the trench opening, the gate having a vertical edge that includes an extended portion, the extended portion extending above the trench opening and being substantially aligned with the trench wall.Type: GrantFiled: December 22, 2009Date of Patent: January 25, 2011Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Sung-Shan Tai, Tiesheng Li, Anup Bhalla, Hong Chang, Moses Ho
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Patent number: 7863995Abstract: A transient voltage suppressing (TVS) circuit with uni-directional blocking and symmetric bi-directional blocking capabilities integrated with an electromagnetic interference (EMI) filter supported on a semiconductor substrate of a first conductivity type. The TVS circuit integrated with the EMI filter further includes a ground terminal disposed on the surface for the symmetric bi-directional blocking structure and at the bottom of the semiconductor substrate for the uni-directional blocking structure and an input and an output terminal disposed on a top surface with at least a Zener diode and a plurality of capacitors disposed in the semiconductor substrate to couple the ground terminal to the input and output terminals with a direct capacitive coupling without an intermediate floating body region.Type: GrantFiled: April 1, 2008Date of Patent: January 4, 2011Assignee: Alpha & Omega Semiconductor Ltd.Inventors: Moses Ho, Madhur Bobde, Mike Chang, Limin Weng
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Publication number: 20100163846Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Inventors: Hamza Yilmaz, Daniel Ng, Lingpeng Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
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Publication number: 20100105182Abstract: Fabricating a semiconductor device includes forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate having a gate top surface that extends substantially above the top substrate surface at least in center region of the trench opening, the gate having a vertical edge that includes an extended portion, the extended portion extending above the trench opening and being substantially aligned with the trench wall.Type: ApplicationFiled: December 22, 2009Publication date: April 29, 2010Inventors: Sung-Shan Tai, Tiesheng Li, Anup Bhalla, Hong Chang, Moses Ho
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Patent number: 7683369Abstract: A structure is disclosed for measuring body pinch resistance Rp of trench MOSFET arrays on a wafer. The trench MOSFET array has a common drain layer of first conductivity type and a 2D-trench MOSFET array atop the common drain layer. The 2D-trench MOSFET array has an interdigitated array of source-body columns and gate trench columns. Each source-body column has a bottom body region of second conductivity type with up-extending finger structures. Each source-body column has top source regions of first conductivity type bridging the finger structures. The structure includes: a) A source-body column wherein each finger structure of the bottom body region has a formed top contact electrode. b) Two gate trench columns flank the source-body column and both have a formed top common gate contact electrode. Upon connection of the structure to external voltage/current measurement devices, Rp can be measured while mimicking the parasitic effect of neighboring trench MOSFETs.Type: GrantFiled: April 10, 2008Date of Patent: March 23, 2010Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Moses Ho, Tiesheng Li, Il Kwan Lee
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Patent number: 7667264Abstract: A semiconductor device comprises a drain, a body in contact with the drain, the body having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a trench extending through the source and the body to the drain, and a gate disposed in the trench, having a gate top surface that extends substantially above the body top surface. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.Type: GrantFiled: September 27, 2004Date of Patent: February 23, 2010Assignee: Alpha and Omega Semiconductor LimitedInventors: Sung-Shan Tai, Tiesheng Li, Anup Bhalla, Hong Chang, Moses Ho
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Publication number: 20090256149Abstract: A structure is disclosed for measuring body pinch resistance Rp of trench MOSFET arrays on a wafer. The trench MOSFET array has a common drain layer of first conductivity type and a 2D-trench MOSFET array atop the common drain layer. The 2D-trench MOSFET array has an interdigitated array of source-body columns and gate trench columns. Each source-body column has a bottom body region of second conductivity type with up-extending finger structures. Each source-body column has top source regions of first conductivity type bridging the finger structures. The structure includes: a) A source-body column wherein each finger structure of the bottom body region has a formed top contact electrode. b) Two gate trench columns flank the source-body column and both have a formed top common gate contact electrode. Upon connection of the structure to external voltage/current measurement devices, Rp can be measured while mimicking the parasitic effect of neighboring trench MOSFETs.Type: ApplicationFiled: April 10, 2008Publication date: October 15, 2009Inventors: Moses Ho, Tiesheng Li, Il Kwan Lee
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Publication number: 20080310065Abstract: A transient voltage suppressing (TVS) circuit with uni-directional blocking and symmetric bi-directional blocking capabilities integrated with an electromagnetic interference (EMI) filter supported on a semiconductor substrate of a first conductivity type. The TVS circuit integrated with the EMI filter further includes a ground terminal disposed on the surface for the symmetric bi-directional blocking structure and at the bottom of the semiconductor substrate for the uni-directional blocking structure and an input and an output terminal disposed on a top surface with at least a Zener diode and a plurality of capacitors disposed in the semiconductor substrate to couple the ground terminal to the input and output terminals with a direct capacitive coupling without an intermediate floating body region.Type: ApplicationFiled: April 1, 2008Publication date: December 18, 2008Inventors: Moses Ho, Madhur Bobde, Mike Chang, Limin Weng
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Publication number: 20080265312Abstract: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.Type: ApplicationFiled: June 30, 2008Publication date: October 30, 2008Inventors: Anup Bhalla, Xiaobin Wang, Moses Ho
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Publication number: 20080090357Abstract: A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.Type: ApplicationFiled: November 9, 2007Publication date: April 17, 2008Inventors: Sung-Shan Tai, Tiesheng Li, Anup Bhalla, Hong Chang, Moses Ho
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Publication number: 20060071268Abstract: A semiconductor device comprises a drain, a body in contact with the drain, the body having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a trench extending through the source and the body to the drain, and a gate disposed in the trench, having a gate top surface that extends substantially above the body top surface. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.Type: ApplicationFiled: September 27, 2004Publication date: April 6, 2006Inventors: Sung-Shan Tai, Tiesheng Li, Anup Bhalla, Hong Chang, Moses Ho