Abstract: An amplifier system includes an instrumentation amplifier arrangement being designed to amplify the difference between two voltage inputs with a defined gain, and to produce a single-ended output referenced to a known reference point. A front end circuit is coupled to the instrumentation amplifier. The front end circuit is configured to include a current clamp to actively limit the current in a gain resistor of the instrumentation amplifier to prevent input currents flowing when the instrumentation amplifier is over-driven.

Abstract: An amplifier system includes an instrumentation amplifier arrangement being designed to amplify the difference between two voltage inputs with a defined gain, and to produce a single-ended output referenced to a known reference point. A front end circuit is coupled to the instrumentation amplifier. The front end circuit is configured to include a current clamp to actively limit the current in a gain resistor of the instrumentation amplifier to prevent input currents flowing when the instrumentation amplifier is over-driven.

Abstract: A circuit for removing non-linearity produced when an amplifier includes a load that results in non-linear current levels is provided. The circuit includes a first transistor element being coupled to one of the differential inputs associated with the amplifier. A second transistor element is coupled to another of the differential inputs associated with the amplifier. The second transistor element is coupled to the current associated with the load. Current passing the collectors of the first and second transistors elements are arranged to be always equal so as to eliminate in the circuit the changes between the base currents of the second transistor element and first transistor element caused by the current associated with the load.

Abstract: A bias circuit is disclosed for use in a temperature compensation system. The bias circuit provides a current that is proportional to a temperature variation raised to an nth power where |n|>1 in accordance with an embodiment. In further embodiments, the bias circuit includes a PTAT current source for providing to a driver-stage amplifier a current that is substantially proportional to absolute temperature, and a CTAT current source for providing a current that is complementary to absolute temperature, wherein the PTAT and CTAT current sources coact to provide a PTAT2 reference current that is proportional to an absolute temperature variation to the nth power wherein |n|>1.

Abstract: A repatterned integrated circuit chip package which balances and/or reduces the package capacitance associated with the gain resistor terminals to reduce the degradation of common mode rejection with frequency.

Abstract: A repatterned integrated circuit chip package which balances and/or reduces the package capacitance associated with the gain resistor terminals to reduce the degradation of common mode rejection with frequency.

Abstract: A current compensation circuit for an amplifier, for example an operational amplifier, having input and output stages coupled at a high-impedance node, compensates for any modulation of current occurring at the high-impedance node. Particularly, the compensation circuit of the present invention reduces the error current at the high-impedance node resulting from a mismatch in beta between PNP and NPN transistors in the output stage, and reduces any error current resulting from the Early voltage effects of transistors in the output stage. In this manner, the present invention serves to substantially isolate the amplifier input stage from the output load, and from any beta mismatch or Early voltage effects in the transistors of the output stage, resulting in greatly improved open-loop gain.

Abstract: A gain stage is disclosed for use in an amplifier which provides an output signal. The gain stage includes a first transistor including a base, an emitter and a collector. The base is coupled to an input signal applied to the gain stage, and the emitter is coupled to a first source of operating potential. The gain stage also includes a second transistor including a base, an emitter and a collector. The collector of the second transistor is coupled to the collector of the first transistor for providing the output signal. The emitter of the second transistor is coupled to a second source of operating potential. The gain stage also includes a level shifter coupled to both the input signal and the base of the second transistor. The level shifter provides level shifting and produces a gain signal responsive to the input signal.

Abstract: A gain stage for use in an amplifier which provides a rail-to-rail output signal. The gain stage includes a first transistor having a base, an emitter and a collector, the base being coupled to an input signal applied to the gain stage and the emitter being coupled to a first source of operating potential; a second transistor having a base, an emitter and a collector, the collector being coupled to the collector of the first transistor for providing the output signal, the emitter being coupled to a second source of operating potential; and a third transistor having a base, an emitter and a collector, the emitter being coupled to the input signal, the base being coupled to a bias voltage, and the collector being coupled to the second operating potential and the base of the second transistor for providing a drive signal thereto allowing the output signal to swing substantially between the first and second sources of operating potential.

Abstract: The invention provides a circuit which substantially cancels the input bias current of an operational amplifier having a cascoded NPN-PNP inmput stage. The compensation circuit comprises three transistors. A first NPN transistor is coupled to the input stage such that its collector is coupled to the positive voltage source of the operational amplifier and its emitter is coupled to the emitter of the dual-collector transistor of the input stage. The second transistor, a PNP transistor, has its base coupled to the base of the dual-collector transistor and its collector coupled to the bases of both of the NPN transistors of the input stage, which form the inputs of the operational amplifier. This PNP transistor's emitter is coupled to the collector of a third transistor which is a dual-collector PNP transistor. A third transistor has an emitter coupled to the positive voltage source of the operational amplifier and a base coupled to the base of the NPN transistor of the compensation circuitry.