Abstract: A processor device is provided with hardware-implemented logic to receive an instruction including a pointer identifier and a pointer change value, the pointer identifier including a pointer address field encoded with an address of a line of memory corresponding to a location of a pointer of a particular one of the one or more cyclic buffers, one or more cushion bits, and a buffer identifier field encoded with a buffer identifier assigned to the particular cyclic buffer. The logic further enables the processor to identify that the instruction is to apply to the particular cyclic buffer based on the buffer identifier, determine that the pointer change value causes a wraparound of the pointer in the particular cyclic buffer, and fix location of the pointer in the particular cyclic buffer based on the wraparound.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that enable dynamic processing of a predefined workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to obtain a workload node, the workload node associated with a first amount of data, the workload node to be executed at a first one of the one or more computational building blocks; an analyzer to: determine whether the workload node is a candidate for early termination; and in response to determining that the workload node is a candidate for early termination, set a flag associated with a tile of the first amount of data; and a dispatcher to, in response to the tile being transmitted from the first one of the one or more computational building blocks to a buffer, stop execution of the workload node.

Abstract: An example apparatus to perform a convolution on an input tensor includes a parameters generator to: generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on a kernel parameter and a layer parameter; and generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on the kernel parameter and the layer parameter; an accelerator interface to configure a hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters; a horizontal Iterator controller to determine when the hardware accelerator circuitry completes the first horizontal iteration of the convolution; and a vertical Iterator controller to determine when the hardware accelerator circuitry completes the first vertical iteration of the convolution.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.

Abstract: An apparatus includes a communication processor to receive configuration information from a producing compute building block; a credit generator to generate a number of credits for the producing compute building block corresponding to the configuration information, the configuration information including characteristics of a buffer; a source identifier to analyze a returned credit to determine whether the returned credit originates from the producing compute building block or a consuming compute building block; and a duplicator to, when the returned credit originates from the producing compute building block, multiply the returned credit by a first factor, the first factor indicative of a number of consuming compute building blocks identified in the configuration information.

Abstract: Apparatus, systems, and methods for a generic firmware-based kernel library mechanism are disclosed. An example apparatus includes a compiler to compile kernels into an executable and linkable format, an image generator to generate library images from executable and linkable format locations, a reducer to retrieve a library image, the library image retrieved starting from a first section of an existing library, the retrieved library image to be used as a platform for developing a new kernel library, a selector to select kernels to include in the new kernel library, one or more libraries organized into a defined number of kernel banks, the kernels combined based on intended application development, and a linker to link a library start function pointer to the library start function, the library start function positioned within the library image, the pointer incorporated in a first section of the library image.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that enable out-of-order pipelined execution of static mapping of a workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to load a first number of credits into memory; a comparator to compare the first number of credits to a threshold number of credits associated with memory availability in a buffer; and a dispatcher to, when the first number of credits meets the threshold number of credits, select a workload node of the workload to be executed at a first one of the one or more computational building blocks.

Abstract: Methods and apparatus to implement efficient communications between components of computing systems are disclosed. An example apparatus includes a message generator to: add a first value associated with a first field of a message to a shift register based on a first push operation, the message including multiple fields, at least two of the fields having different bit widths; and add a second value associated with a second field of the message to the shift register based on a second push operation, the second value to be adjacent the first value in the shift register in accordance with a structure of the message. The example apparatus further includes a communications interface to transmit content stored in the shift register to a hardware device via a bus having a width corresponding to a width of the shift register, the content including the message.

Abstract: A lice comb (10) comprising a housing (12) having a planar lower wall portion (14), an upper wall portion (16) and a side wall portion (18). A comb unit (20) comprising a blade (22) having a plurality of teeth (24) is moveable from a retracted position, in which the blade (22) is parallel to the lower wall portion (14), and an extended position, in which the blade (22) extends at an angle away from the lower wall portion (14). A fan unit is provided within the housing (12) such that the fan unit operates to draw air inwardly through an opening (30) in the lower wall portion (14) adjacent the comb unit (20). When the blade (20) is in the extended position, the housing (12) may be moved to draw the teeth (24) through hair such that lice captured by the teeth (24) are drawn in through the opening (30).

Abstract: A lice removal device (10) comprising a main housing (12) including a first aperture (15) at a first end (14) thereof and a second aperture (17) at a second end (16) thereof. A fan unit (18) is provided within the main housing (12) to draw air in through the first aperture (15) and expel air outwardly through the second aperture (17) A comb unit (43) is securable to the first end of the main housing (12), the comb unit (34) comprising a comb housing (36) and a blade unit (38). The blade unit (38) includes a first side member (46) having a plurality of teeth (44) extending outwardly therefrom and a second side member (48) located adjacent and parallel to the first side member (46) to define an elongate opening (50) such that air is drawn across a first side of the teeth (44) and into the elongate opening (50).

Abstract: A lice comb (10) comprising a main housing (12) including a first aperture (15) at a first end (14) thereof and a second aperture (17) at a second end (16) thereof. A fan unit (18) draw airs in through the first aperture (15) and expels air outwardly through the second aperture (17). A comb module (38) is rotatably secured to a comb support unit (34) adjacent a first end of the main housing (12). The comb module (38) comprises a comb body (46) and a tine module (48) having a plurality of teeth (44). The comb body (46) includes a channel (52) extending from a first longitudinal side adjacent the tine module (48) to a second longitudinal side thereof and a tine slot (54) is located adjacent the first end of the channel (52) to receive the tine module (48) such that air drawn in through the channel (52) passes across a first surface of the teeth (44).

Abstract: A convolutional neural network (CNN) accelerator, including: a CNN circuit for performing a multiple-layer CNN computation, wherein the multiple layers are to receive an input feature according to an input feature map (IFM) and a weight matrix per output feature, wherein an output of a first layer provides an input for a next layer; and a mapping circuit to access a three-dimensional input matrix stored as a Z-major matrix; wherein the CNN circuit is to perform an inner-product direct convolution on the Z-major matrix, wherein the direct convolution lacks a lowering operation.

Abstract: A processor device is provided with hardware-implemented logic to receive an instruction including a pointer identifier and a pointer change value, the pointer identifier including a pointer address field encoded with an address of a line of memory corresponding to a location of a pointer of a particular one of the one or more cyclic buffers, one or more cushion bits, and a buffer identifier field encoded with a buffer identifier assigned to the particular cyclic buffer. The logic further enables the processor to identify that the instruction is to apply to the particular cyclic buffer based on the buffer identifier, determine that the pointer change value causes a wraparound of the pointer in the particular cyclic buffer, and fix location of the pointer in the particular cyclic buffer based on the wraparound.

Abstract: Methods, systems, and computer readable media can be operable to facilitate an analysis and control of video quality of experience (VQoE) of services delivered to one or more client devices. A content version segment may be selected for delivery to a client device based upon an estimation of the video quality experienced by the client device and the bandwidth available for delivering content to the client device. Video quality estimation may be based upon information associated with the encoding of a media stream coupled with one or more parameters of the client device receiving the media stream. Video quality estimation for one or more client devices may be aggregated and displayed to a service operator and/or may be used to inform content selection decisions in an adaptive bit-rate delivery method.

Abstract: A processor includes a decode unit to decode a packed finite impulse response (FIR) filter instruction that indicates one or more source packed data operands, a plurality of FIR filter coefficients, and a destination storage location. The source operand(s) include a first number of data elements and a second number of additional data elements. The second number is one less than a number of FIR filter taps. An execution unit, in response to the packed FIR filter instruction being decoded, is to store a result packed data operand. The result packed data operand includes the first number of FIR filtered data elements that each is to be based on a combination of products of the plurality of FIR filter coefficients and a different corresponding set of data elements from the one or more source packed data operands, which is equal in number to the number of FIR filter taps.

Abstract: A lice removal device (10) comprising a main housing (12) including a first aperture (15) at a first end (14) thereof and a second aperture (17) at a second end (16) thereof. A fan unit (18) is provided within the main housing (12) to draw air in through the first aperture (15) and expel air outwardly through the second aperture (17) A comb unit (43) is securable to the first end of the main housing (12), the comb unit (34) comprising a comb housing (36) and a blade unit (38). The blade unit (38) includes a first side member (46) having a plurality of teeth (44) extending outwardly therefrom and a second side member (48) located adjacent and parallel to the first side member (46) to define an elongate opening (50) such that air is drawn across a first side of the teeth (44) and into the elongate opening (50).

Abstract: Systems and methods may provide for establishing an out-of-band (OOB) channel between a local wireless interface and a remote backend receiver, and receiving information from a peripheral device via the local wireless interface. Additionally, the information may be sent to the backend receiver via the OOB channel, wherein the OOB channel bypasses a local operating system. In one example, a secure Bluetooth stack is used to receive the information from the peripheral device.

Abstract: A processor includes a decode unit to decode a packed finite impulse response (FIR) filter instruction that indicates one or more source packed data operands, a plurality of FIR filter coefficients, and a destination storage location. The source operand(s) include a first number of data elements and a second number of additional data elements. The second number is one less than a number of FIR filter taps. An execution unit, in response to the packed FIR filter instruction being decoded, is to store a result packed data operand. The result packed data operand includes the first number of FIR filtered data elements that each is to be based on a combination of products of the plurality of FIR filter coefficients and a different corresponding set of data elements from the one or more source packed data operands, which is equal in number to the number of FIR filter taps.