Patents by Inventor Motohiro Sakai

Motohiro Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200409778
    Abstract: A storage control device includes: an auxiliary cache memory that is a nonvolatile memory; a volatile memory; and a processor configured to execute a saving control process after a predetermined failure occurs, the saving control process being configured to (a) cause a writing control process to stop writing of data stored in the auxiliary cache memory to the storage medium, (b) secure, in the auxiliary cache memory, a storage region for storing the management information of the volatile memory, (c) generate a copy of management information of the volatile memory in the storage region, and (d) cause the writing control process to execute control to write first data stored in the volatile memory to the auxiliary cache memory or the storage medium based on the management information of the auxiliary cache memory.
    Type: Application
    Filed: June 3, 2020
    Publication date: December 31, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Keima ABE, Motohiro Sakai, Takuro Kumabe
  • Patent number: 10712966
    Abstract: A storage control device includes a processor configured to receive access information indicating a start position and an end position of an access area in a first volume. The processor is configured to determine, based on one or more pieces of the received access information, whether a number of blocks in a cache area is reduced as a whole by changing a position of data in the first volume. The blocks are used in response to an access to the access area and correspond to one or more unit areas in the first volume. The one or more unit areas include the access area. The processor is configured to change the position of the data in the first volume upon determining that the number of the blocks in the cache area is reduced as a whole by changing the position of the data in the first volume.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 14, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Keima Abe, Takuro Kumabe, Akihito Kobayashi, Motohiro Sakai
  • Patent number: 10664393
    Abstract: A memory includes a plurality of pages used as a cache area. A processor allocates a first storage resource to a first link indicating a first page group of the plurality of pages, and a second storage resource to a second link indicating a second page group of the plurality of pages. The processor uses the first and the second links, and processes access requests for accessing to the first and the second storage resources, in parallel.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: May 26, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Takuro Kumabe, Motohiro Sakai, Keima Abe
  • Patent number: 10628048
    Abstract: A storage control device includes a processor configured to receive from a host device a write request for writing data into a memory device. The processor is configured to try to write the data into a cache memory. The processor is configured to select an operation mode of a write process for the write request from among a first mode and a second mode on the basis of whether a cache hit or a cache miss occurs at the trial. The processor is configured to return a response to the host device upon completion of writing the data into the cache memory without waiting for completion of the write process when the write process is performed in the first mode. The processor is configured to return a response to the host device upon completion of the write process when the write process is performed in the second mode.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: April 21, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Takuro Kumabe, Motohiro Sakai, Keima Abe
  • Patent number: 10487183
    Abstract: The present invention has as its object the provision of a method of bonding substrates, which can bond two substrates, at least one of which has warpage and undulation of a bonding surface, in a high adhesion state and a method of producing a microchip.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: November 26, 2019
    Assignee: Ushio Denki Kabushiki Kaisha
    Inventors: Fumitoshi Takemoto, Shinji Suzuki, Motohiro Sakai, Kenichi Hirose
  • Publication number: 20190300662
    Abstract: The present invention has as its object the provision of a method of bonding substrates, which can bond two substrates, at least one of which has warpage and undulation of a bonding surface, in a high adhesion state and a method of producing a microchip.
    Type: Application
    Filed: June 27, 2017
    Publication date: October 3, 2019
    Applicant: Ushio Denki Kabushiki Kaisha
    Inventors: Fumitoshi TAKEMOTO, Shinji SUZUKI, Motohiro SAKAI, Kenichi HIROSE
  • Patent number: 10346070
    Abstract: When an access process has been requested for a storage apparatus, a registration unit determines an access priority of the requested access process and registers an entry corresponding to the requested access process in a queue corresponding to the determined access priority out of a plurality of queues that are each provided for a different access priority. An instruction unit checks the plurality of queues at intermittent check timing, fetches, at each check timing, one entry from each queue, out of the plurality of queues, in which entries are registered, and instructs the storage apparatus to execute access processes corresponding to the fetched entries.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: July 9, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Shinichiro Matsumura, Motohiro Sakai, Takahiro Ohyama, Takuro Kumabe, Akihito Kobayashi
  • Publication number: 20190155730
    Abstract: A memory includes a plurality of pages used as a cache area. A processor allocates a first storage resource to a first link indicating a first page group of the plurality of pages, and a second storage resource to a second link indicating a second page group of the plurality of pages. The processor uses the first and the second links, and processes access requests for accessing to the first and the second storage resources, in parallel.
    Type: Application
    Filed: September 20, 2018
    Publication date: May 23, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Takuro Kumabe, Motohiro Sakai, Keima ABE
  • Patent number: 10234929
    Abstract: A first control apparatus includes a first memory unit including a local cache, a first power supply that supplies electric power to the first memory unit, and a control unit. The control unit controls a write into a memory device by a write-back method, using the local cache. The control unit mirrors data of the local cache in a mirror cache of a second control apparatus. The control unit determines whether the mirror cache is included in a second memory unit that receives electric power from a second power supply of the second control apparatus, upon detecting an abnormal state of a battery for supplying electric power to the second memory unit in case of power outage of the second power supply. The second memory unit switches write control for the memory device to a write-through method, when the second memory unit includes the mirror cache.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: March 19, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Hidefumi Kobayashi, Satoshi Yazawa, Atsushi Igashira, Wataru Iizuka, Motohiro Sakai, Akihito Kobayashi, Shinichiro Matsumura, Kenji Kobayashi
  • Publication number: 20190018609
    Abstract: A storage control device includes a processor configured to receive access information indicating a start position and an end position of an access area in a first volume. The processor is configured to determine, based on one or more pieces of the received access information, whether a number of blocks in a cache area is reduced as a whole by changing a position of data in the first volume. The blocks are used in response to an access to the access area and correspond to one or more unit areas in the first volume. The one or more unit areas include the access area. The processor is configured to change the position of the data in the first volume upon determining that the number of the blocks in the cache area is reduced as a whole by changing the position of the data in the first volume.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 17, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Keima ABE, Takuro Kumabe, Akihito Kobayashi, Motohiro Sakai
  • Publication number: 20180181318
    Abstract: A storage control device includes a processor configured to receive from a host device a write request for writing data into a memory device. The processor is configured to try to write the data into a cache memory. The processor is configured to select an operation mode of a write process for the write request from among a first mode and a second mode on the basis of whether a cache hit or a cache miss occurs at the trial. The processor is configured to return a response to the host device upon completion of writing the data into the cache memory without waiting for completion of the write process when the write process is performed in the first mode. The processor is configured to return a response to the host device upon completion of the write process when the write process is performed in the second mode.
    Type: Application
    Filed: November 21, 2017
    Publication date: June 28, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Takuro Kumabe, Motohiro Sakai, Keima Abe
  • Publication number: 20180141280
    Abstract: Disclosed herein is a method of bonding substrates, a microchip, and a method of manufacturing the microchip capable of joining two substrates in a higher adhered state even when at least one of the substrate has a warpage or a roll. A method of bonding a first substrate and a second substrate each of which is made of glass or a resin comprises: a surface activating step for activating each of joining surfaces of the first substrate and the second substrate; and a pressurizing step for pressurizing the first substrate and the second substrate in a state that the first substrate and the second substrate are stacked such that respective joining surfaces contact each other. The joining surface of the first substrate and/or the joining surface of the second substrate are constituted with a plurality of joining regions segmented to be separate from one another by a segmenting recessed portion.
    Type: Application
    Filed: November 15, 2017
    Publication date: May 24, 2018
    Applicant: USHIO DENKI KABUSHIKI KAISHA
    Inventors: Motohiro SAKAI, Shinji SUZUKI, Fumitoshi TAKEMOTO, Kenichi HIROSE
  • Patent number: 9904474
    Abstract: A control device includes a processor. The processor is configured to collect plural types of performance information regarding a first data unit. The processor is configured to determine, on basis of the collected plural types of performance information, whether to transfer the first data unit from a first storage device which is under control of a first controller to a second storage device which is positioned as higher than the first storage device. The processor is configured to transfer the first data unit from the first storage device to the second storage device depending on a result of the determination.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: February 27, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Takuro Kumabe, Akihito Kobayashi, Motohiro Sakai, Shinichiro Matsumura, Takahiro Ohyama
  • Patent number: 9734087
    Abstract: A control unit stores data used in a process to a shared cache memory. The control unit provides a shared queue in a memory space of the shared cache memory and performs LRU control with the use of the shared queue. The control unit also provides a local queue in the memory space of the shared cache memory. The control unit enqueues a CBE (management information) for a cache page used by a core in a process to the local queue. The control unit dequeues a plurality of CBEs from the local queue upon satisfaction of a predetermined condition, and enqueues the dequeued CBEs to the shared queue.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: August 15, 2017
    Inventors: Takuro Kumabe, Akihito Kobayashi, Motohiro Sakai, Shinichiro Matsumura, Takahiro Ohyama
  • Publication number: 20170147244
    Abstract: When an access process has been requested for a storage apparatus, a registration unit determines an access priority of the requested access process and registers an entry corresponding to the requested access process in a queue corresponding to the determined access priority out of a plurality of queues that are each provided for a different access priority. An instruction unit checks the plurality of queues at intermittent check timing, fetches, at each check timing, one entry from each queue, out of the plurality of queues, in which entries are registered, and instructs the storage apparatus to execute access processes corresponding to the fetched entries.
    Type: Application
    Filed: October 6, 2016
    Publication date: May 25, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Shinichiro Matsumura, Motohiro Sakai, Takahiro Ohyama, Takuro Kumabe, Akihito Kobayashi
  • Publication number: 20170123699
    Abstract: A storage control device is one of a plurality of control devices each controlling different storage areas. The storage control device includes a memory and a processor coupled to the memory. The processor is configured to acquire an allocation request for allocating a storage area to a first virtual volume. The processor is configured to allocate a first storage area to the first virtual volume upon acquiring the allocation request. The first storage area is controlled by a first control device among the plurality of control devices. The first control device controls the first virtual volume.
    Type: Application
    Filed: October 20, 2016
    Publication date: May 4, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Takahiro Ohyama, Akihito Kobayashi, Motohiro Sakai, Shinichiro Matsumura, Takuro Kumabe
  • Patent number: 9632950
    Abstract: An apparatus includes a first cache memory, a second cache memory, and a processor coupled to the first cache memory and the second cache memory, and configured to store data in the second cache memory, the data being deleted from the first cache memory, store first data stored in a first address of the storage device, in the second cache memory, in case where the first address is included in first management information and is not included in second management information, according to a request for access to the first address of the storage device, the first management information including an address in the storage device of specific data stored in the storage device, and the second management information including an address in the storage device of data stored in both of the second cache memory and the storage device, and register the first address in the second management information.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: April 25, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shinichiro Matsumura, Akihito Kobayashi, Motohiro Sakai, Takahiro Ohyama, Takuro Kumabe
  • Patent number: 9606735
    Abstract: An operational management server manages a storage device that includes a plurality of types of disks having different performances. A setting unit sets a target value of a performance to a volume produced by using the different types of the disks. An allocation rate management unit determines allocation rates of the respective types of the disks included in the volume on the basis of the target value set by the setting unit, and instructs the storage device to reproduce the volume in accordance with the determined allocation rates.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: March 28, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shinya Hamano, Toshiharu Makida, Kiyoshi Sugioka, Motohiro Sakai
  • Publication number: 20160321175
    Abstract: A first control apparatus includes a first memory unit including a local cache, a first power supply that supplies electric power to the first memory unit, and a control unit. The control unit controls a write into a memory device by a write-back method, using the local cache. The control unit mirrors data of the local cache in a mirror cache of a second control apparatus. The control unit determines whether the mirror cache is included in a second memory unit that receives electric power from a second power supply of the second control apparatus, upon detecting an abnormal state of a battery for supplying electric power to the second memory unit in case of power outage of the second power supply. The second memory unit switches write control for the memory device to a write-through method, when the second memory unit includes the mirror cache.
    Type: Application
    Filed: March 23, 2016
    Publication date: November 3, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Hidefumi Kobayashi, SATOSHI YAZAWA, Atsushi IGASHIRA, Wataru Iizuka, Motohiro Sakai, Akihito Kobayashi, Shinichiro Matsumura, Kenji KOBAYASHI
  • Publication number: 20160085446
    Abstract: A control device includes a processor. The processor is configured to collect plural types of performance information regarding a first data unit. The processor is configured to determine, on basis of the collected plural types of performance information, whether to transfer the first data unit from a first storage device which is under control of a first controller to a second storage device which is positioned as higher than the first storage device. The processor is configured to transfer the first data unit from the first storage device to the second storage device depending on a result of the determination.
    Type: Application
    Filed: August 10, 2015
    Publication date: March 24, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Takuro Kumabe, Akihito Kobayashi, Motohiro Sakai, Shinichiro Matsumura, Takahiro Ohyama