Patents by Inventor Motohito Hori
Motohito Hori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128241Abstract: A semiconductor device includes: an insulated circuit substrate including a conductive plate on a top surface side; a semiconductor chip mounted on the conductive plate; and an external connection terminal electrically connected to the semiconductor chip and including an inner-side conductor layer, an outer-side conductor layer provided at a circumference of the inner-side conductor layer, and an insulating layer interposed between the inner-side conductor layer and the outer-side conductor layer.Type: ApplicationFiled: August 23, 2023Publication date: April 18, 2024Applicant: FUJI ELECTRIC CO., LTD.Inventors: Akira HIRAO, Yoshinari IKEDA, Motohito HORI
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Publication number: 20240128880Abstract: A power converter includes a capacitor and a substrate on which a plurality of switching elements for power conversion are mounted. The power converter includes a cooler for cooling the plurality of switching elements and a housing that accommodates the capacitor, the substrate, and the cooler. The power converter includes a power connector exposed from the housing and an output connector exposed from the housing. The power converter includes a plurality of lines that include a plurality of power lines each electrically connected to the capacitor, given switching elements, and the power connector. The plurality of lines include a plurality of output lines each electrically connected to given switching elements and the output connector. At least one among the plurality of lines is a line that includes a conductive pattern formed on the substrate.Type: ApplicationFiled: December 26, 2023Publication date: April 18, 2024Inventors: Yuji SUZUKI, Motohito HORI, Akio TOBA, Ikuya SATO, Yasuhito TANAKA, Masamichi IWASAKI, Masaaki AJIMA, Nobuaki OHGURI
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Patent number: 11949338Abstract: A power converter includes a positive busbar electrically connected to a positive terminal and the first capacitor electrode, and includes a negative busbar electrically connected to a negative terminal and the second capacitor electrode. The power converter includes output busbars each electrically connected to a given output terminal among multiple output terminals, a given high-side switching element among a plurality of high-side switching elements, and a given low-side switching element among a plurality of low-side switching elements. The power converter includes a cooler that cools the high-side switching elements and the low-side switching elements. The power converter includes a housing that accommodates a supply tube and a discharge tube. The positive terminal, the negative terminal, the output terminals, the inlet port, and the outlet port are exposed on the housing. The inlet port, the outlet port, the supply tube, and the discharge tube are separate members from the housing.Type: GrantFiled: February 23, 2022Date of Patent: April 2, 2024Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yuji Suzuki, Motohito Hori, Akio Toba, Ikuya Sato, Yasuhito Tanaka, Masamichi Iwasaki, Masaaki Ajima, Nobuaki Ohguri
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Patent number: 11894774Abstract: A power converter includes a capacitor and a substrate on which a plurality of switching elements for power conversion are mounted. The power converter includes a cooler for cooling the plurality of switching elements and a housing that accommodates the capacitor, the substrate, and the cooler. The power converter includes a power connector exposed from the housing and an output connector exposed from the housing. The power converter includes a plurality of lines that include a plurality of power lines each electrically connected to the capacitor, given switching elements, and the power connector. The plurality of lines include a plurality of output lines each electrically connected to given switching elements and the output connector. At least one among the plurality of lines is a line that includes a conductive pattern formed on the substrate.Type: GrantFiled: February 23, 2022Date of Patent: February 6, 2024Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yuji Suzuki, Motohito Hori, Akio Toba, Ikuya Sato, Yasuhito Tanaka, Masamichi Iwasaki, Masaaki Ajima, Nobuaki Ohguri
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Publication number: 20240006287Abstract: A semiconductor device includes an insulated circuit substrate, a semiconductor chip, a printed circuit board, an interposer, and a sealing member, the interposer including a plurality of post electrodes each having one end bonded to the semiconductor chip via a solder layer, an insulating layer provided to be separately opposed to the semiconductor chip and provided with a first penetration hole filled with part of the solder layer, and a conductor layer provided to be opposed to the printed circuit board and connected to another end of each of the post electrodes via the insulating layer.Type: ApplicationFiled: April 25, 2023Publication date: January 4, 2024Applicant: FUJI ELECTRIC CO., LTD.Inventors: Motohito HORI, Yoshinari IKEDA, Akira HIRAO
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Publication number: 20230411313Abstract: A semiconductor device includes: an insulated circuit substrate; a semiconductor chip provided on the insulated circuit substrate; a first external connection terminal provided on the insulated circuit substrate; a relay terminal provided on the insulated circuit substrate; a printed circuit board arranged over the semiconductor chip and connected to the first external connection terminal and the relay terminal; and a first snubber circuit provided on the printed circuit board and having one end connected to the first external connection terminal via the printed circuit board and another end connected to the relay terminal via the printed circuit board.Type: ApplicationFiled: April 24, 2023Publication date: December 21, 2023Applicant: FUJI ELECTRIC CO., LTD.Inventors: Akira HIRAO, Yoshinari IKEDA, Motohito HORI
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Publication number: 20230369142Abstract: A semiconductor device includes a first input conductive plate on which a plurality of first semiconductor chips arranged in a first direction, a first output conductive plate extending in the first direction and being provided adjacent to the first input conductive plate, a case having first to fourth side walls for accommodating the first input conductive plate and the first output conductive plate, first main current wiring members, each of which connects one of the first output electrodes to a front surface of the first output conductive plate, a first detection terminal disposed in the first side wall, and a first detection wiring member connecting the front surface of the first output conductive plate to the first detection terminal. The first output conductive plate is disposed closer to the first side wall than is the first input conductive plate.Type: ApplicationFiled: March 9, 2023Publication date: November 16, 2023Applicant: FUJI ELECTRIC CO., LTD.Inventors: Motohito HORI, Yoshinari IKEDA, Takaaki TANAKA, Qichen WANG
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Publication number: 20230260859Abstract: A semiconductor device includes a semiconductor module that includes: an insulating circuit board, a semiconductor chip provided on a main surface of the insulating circuit board, and an external connection terminals provided on the main surface of the insulating circuit board; an external printed circuit board provided so as to face a main surface of the semiconductor module, the external printed circuit board having a through hole into which the external connection terminal is inserted; and an elastic member provided between the main surface of the semiconductor module and the external printed circuit board so as to apply a pressing force to the main surface of the semiconductor module.Type: ApplicationFiled: January 3, 2023Publication date: August 17, 2023Applicant: Fuji Electric Co., Ltd.Inventors: Motohito HORI, Yoshinari IKEDA, Akira HIRAO
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Publication number: 20230187311Abstract: A semiconductor module includes a conductor layer, an insulating plate, a circuit pattern layer, and semiconductor chips disposed in this order. The conductor layer has a first through hole. The insulating plate has a second through hole having an opening size larger than the first through hole at a location facing the first through hole. The circuit pattern layer has an opening having an opening size larger than the second through hole at a location facing the second through hole. When the semiconductor module is connected to a cooling member, heat transfer medium is disposed between the conductor layer and the cooling member. A screw member is inserted into the opening and second and first through holes and screwed into a screw attachment hole. The screw member presses an area around the first through hole inside the second through hole toward the cooling member.Type: ApplicationFiled: October 25, 2022Publication date: June 15, 2023Applicant: FUJI ELECTRIC CO., LTD.Inventors: Motohito HORI, Yoshinari IKEDA
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Patent number: 11658231Abstract: A semiconductor device having a semiconductor module. The semiconductor module includes first and second conductor layers facing each other, a first semiconductor element provided between the first and second conductor layers, positive and negative electrode terminals respectively provided on edge portions of the first and second conductor layers at a first side of the semiconductor module in a top view of the semiconductor module, control wiring that is electrically connected to the first control electrode, and that extends out of the first and second conductor layers at a second side of the semiconductor module that is opposite to the first side in the top view, and a control terminal that is electrically connected to the control wiring, that is positioned outside the first and second conductor layers in the top view, and that has an end portion that is aligned with the positive and negative electrode terminals.Type: GrantFiled: October 30, 2020Date of Patent: May 23, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventors: Motohito Hori, Yoshinari Ikeda, Akira Hirao, Tsunehiro Nakajima
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Patent number: 11605582Abstract: A semiconductor device includes a wiring board that includes a first insulating layer, a first conductive layer arranged over the first insulating layer, a second conductive layer arranged under the first insulating layer, the wiring board further including a magnetic layer that is arranged between the first insulating layer and the first or second conductive layer and that has a higher specific magnetic permeability than the first and second conductive layers, and a carbon layer that is arranged between the first insulating layer and the first or second conductive layer and that has a higher thermal conductivity in a planary direction than the first and second conductive layers; a semiconductor chip electrically connected to the first and second conductive layers; and an insulating circuit board arranged separately from the wiring board and that has the semiconductor chip mounted thereon.Type: GrantFiled: August 2, 2021Date of Patent: March 14, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takahiro Mitsumoto, Akira Hirao, Motohito Hori
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Patent number: 11545409Abstract: A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern on an upper surface of the insulating plate and a heat dissipating plate on a lower surface of the insulating plate. The module further includes a semiconductor device having upper and lower surfaces, and including a collector electrode on the device upper surface, an emitter electrode and a gate electrode on the device lower surface, and the emitter electrode and the gate electrode each being bonded to an upper surface of the circuit pattern via a bump, and a block electrode bonded to the collector electrode. The block electrode includes a flat plate portion covering over the semiconductor device, and a pair of projecting portions projecting toward the circuit pattern from both ends of the flat plate portion in a thickness direction orthogonal to a surface of the insulating plate, and being bonded to the circuit pattern.Type: GrantFiled: January 5, 2021Date of Patent: January 3, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventors: Ryoichi Kato, Yoshinari Ikeda, Tatsuo Nishizawa, Motohito Hori, Eiji Mochizuki
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Publication number: 20220406689Abstract: A semiconductor device includes: an insulated circuit substrate including a conductive plate on a top surface side; a semiconductor chip mounted on the conductive plate; a printed circuit board provided over and electrically connected to the semiconductor chip; a first external connection terminal electrically connected to the conductive plate and extending upward from the conductive plate; a first conductive block provided to surround an outer circumference of the first external connection terminal in an insulated state; and a sealing member provided to seal the semiconductor chip, the printed circuit board, and the first conductive block.Type: ApplicationFiled: May 24, 2022Publication date: December 22, 2022Applicant: FUJI ELECTRIC CO., LTD.Inventors: Motohito HORI, Yoshinari IKEDA, Akira HIRAO
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Publication number: 20220406690Abstract: A semiconductor device includes: an insulated circuit substrate including first and second conductive layers on a top surface side; a first semiconductor chip mounted on the first conductive layer; a second semiconductor chip mounted on the second conductive layer; a printed circuit board including a first lower-side wiring layer arranged to be opposed to the first semiconductor chip, and a second lower-side wiring layer arranged to be opposed to the second semiconductor chip, the printed circuit board being provided with a curved part curved toward the insulated circuit substrate; a first connection member arranged to connect the first semiconductor chip with the first lower-side wiring layer; a second connection member arranged to connect the second semiconductor chip with the second lower-side wiring layer; and a third connection member arranged to connect the first conductive layer with the second lower-side wiring layer at the curved part.Type: ApplicationFiled: April 28, 2022Publication date: December 22, 2022Applicant: FUJI ELECTRIC CO., LTD.Inventors: Motohito HORI, Yoshinari IKEDA, Akio TOBA, Michio TAMATE, Ikuya SATO
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Patent number: 11521925Abstract: A semiconductor module, including a board that has first and second conductive plates located side by side on a first insulating plate, a first external connection terminal located on the first conductive plate, first and second semiconductor chips respectively disposed on the first and second conductive plates, and a printed-circuit board including a second insulating plate and first and second wiring boards located on a first principal plane of the second insulating plate. The first wiring board electrically connects an upper surface electrode of the first semiconductor chip and a relay area on the second conductive plate. The second wiring board is electrically connected to an upper surface electrode of the second semiconductor chip. The semiconductor module further includes a second external connection terminal electrically connected to an end portion of the second wiring board and formed on the second principal plane of the second insulating plate.Type: GrantFiled: October 23, 2020Date of Patent: December 6, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventors: Akira Hirao, Yoshinari Ikeda, Motohito Hori
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Patent number: 11417634Abstract: A semiconductor module having a first metal wiring board, a second metal wiring board, a third metal wiring board, and a first semiconductor element and a second semiconductor element that each include an emitter electrode and a collector electrode. The second metal wiring board is disposed over a principal surface of the first metal wiring board with an insulation material therebetween. The third metal wiring board has a principal surface thereof facing the first metal wiring board. The first and second semiconductor elements are disposed to face directions opposite to each other. The collector electrodes of the first and second semiconductor elements respectively face the principal surfaces of the first and third metal wiring boards. The emitter electrodes of the first and second semiconductor elements are respectively connected to the principal surfaces of the third and second metal wiring boards.Type: GrantFiled: September 25, 2020Date of Patent: August 16, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventors: Motohito Hori, Yoshinari Ikeda
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Publication number: 20220181981Abstract: A power converter includes a positive busbar electrically connected to a positive terminal and the first capacitor electrode, and includes a negative busbar electrically connected to a negative terminal and the second capacitor electrode. The power converter includes output busbars each electrically connected to a given output terminal among multiple output terminals, a given high-side switching element among a plurality of high-side switching elements, and a given low-side switching element among a plurality of low-side switching elements. The power converter includes a cooler that cools the high-side switching elements and the low-side switching elements. The power converter includes a housing that accommodates a supply tube and a discharge tube. The positive terminal, the negative terminal, the output terminals, the inlet port, and the outlet port are exposed on the housing. The inlet port, the outlet port, the supply tube, and the discharge tube are separate members from the housing.Type: ApplicationFiled: February 23, 2022Publication date: June 9, 2022Inventors: Yuji SUZUKI, Motohito HORI, Akio TOBA, Ikuya SATO, Yasuhito TANAKA, Masamichi IWASAKI, Masaaki AJIMA, Nobuaki OHGURI
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Publication number: 20220181980Abstract: A power converter includes a capacitor and a substrate on which a plurality of switching elements for power conversion are mounted. The power converter includes a cooler for cooling the plurality of switching elements and a housing that accommodates the capacitor, the substrate, and the cooler. The power converter includes a power connector exposed from the housing and an output connector exposed from the housing. The power converter includes a plurality of lines that include a plurality of power lines each electrically connected to the capacitor, given switching elements, and the power connector. The plurality of lines include a plurality of output lines each electrically connected to given switching elements and the output connector. At least one among the plurality of lines is a line that includes a conductive pattern formed on the substrate.Type: ApplicationFiled: February 23, 2022Publication date: June 9, 2022Inventors: Yuji SUZUKI, Motohito HORI, Akio TOBA, Ikuya SATO, Yasuhito TANAKA, Masamichi IWASAKI, Masaaki AJIMA, Nobuaki OHGURI
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Publication number: 20220077044Abstract: A semiconductor device includes a wiring board that includes a first insulating layer, a first conductive layer arranged over the first insulating layer, a second conductive layer arranged under the first insulating layer, the wiring board further including a magnetic layer that is arranged between the first insulating layer and the first or second conductive layer and that has a higher specific magnetic permeability than the first and second conductive layers, and a carbon layer that is arranged between the first insulating layer and the first or second conductive layer and that has a higher thermal conductivity in a planary direction than the first and second conductive layers; a semiconductor chip electrically connected to the first and second conductive layers; and an insulating circuit board arranged separately from the wiring board and that has the semiconductor chip mounted thereon.Type: ApplicationFiled: August 2, 2021Publication date: March 10, 2022Applicant: Fuji Electric Co., Ltd.Inventors: Takahiro MITSUMOTO, Akira HIRAO, Motohito HORI
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Patent number: 11251163Abstract: A semiconductor device having a semiconductor module that includes a first conductor layer and a second conductor layer facing each other, a group of semiconductor elements that are formed between the first and second conductor layers, and are connected to the second conductor layer respectively via a group of conductor blocks, and a circuit board having one end portion thereof located in a space between the semiconductor elements and the second conductor layer. Each semiconductor element includes first and second main electrodes respectively formed on first and second main surfaces thereof, and a control electrode that is formed on the second main surface. The first main electrode is electrically connected to the first conductor layer. The second main electrode is electrically connected to the second conductor layer via the respective conductor block. The circuit board includes a first wiring layer electrically connected to the control electrodes of the semiconductor elements.Type: GrantFiled: October 29, 2020Date of Patent: February 15, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventors: Motohito Hori, Yoshinari Ikeda, Akira Hirao