Abstract: A vehicle control system includes a first electronic control apparatus and a second electronic control apparatus. The first electronic control apparatus includes a first controller, a first communication circuit, and a housing. The first controller is configured to execute a first operating system that operates a first application. The housing is configured to contain the first controller and the first communication circuit. The second electronic control apparatus includes a second controller and a second communication circuit. The second controller is configured to execute a second operating system that operates a second application. The second communication circuit is configured to perform data communication with the first communication circuit.

Abstract: An in-vehicle system includes a primary CPU that is mounted in a vehicle and operates on a general-purpose OS, and a peripheral device that is controlled by the primary CPU. The in-vehicle system further includes a secondary CPU that operates on a real-time OS. The secondary CPU performs an initialization process on the peripheral device at startup, and then assigns control of the peripheral device to the primary CPU.

Abstract: A data processing device includes: a first controller requiring a first activation time; a second controller requiring a second activation time, which is shorter than the first activation time; and a data processor for switching a mode, in which data is processed, between a first processing mode without collaboration with the first controller, and a second processing mode in collaboration with the first controller. The data processor processes data in the first processing mode after completing the activation of the second controller and before completing the activation of the first controller; processes data in the second processing mode after completing the activation of the first controller; and processes data in the first processing mode after a fault occurs in the first controller.

Abstract: An in-vehicle system includes a primary CPU that is mounted in a vehicle and operates on a general-purpose OS, and a peripheral device that is controlled by the primary CPU. The in-vehicle system further includes a secondary CPU that operates on a real-time OS. The secondary CPU performs an initialization process on the peripheral device at startup, and then assigns control of the peripheral device to the primary CPU.

Abstract: A data processing device includes: a first controller requiring a first activation time; a second controller requiring a second activation time, which is shorter than the first activation time; and a data processor for switching a mode, in which data is processed, between a first processing mode without collaboration with the first controller, and a second processing mode in collaboration with the first controller. The data processor processes data in the first processing mode after completing the activation of the second controller and before completing the activation of the first controller; processes data in the second processing mode after completing the activation of the first controller; and processes data in the first processing mode after a fault occurs in the first controller.

Abstract: A navigation device for a vehicle includes: a memory device including a NAND type flash memory for storing a predetermined program and a boot program and a controller for searching a failure block in the flash memory and managing a corresponding relation between a logic block and a physical block with eliminating failure blocks; a back-up power source; a power source switch for coupling the memory device with the back-up power source; a power source for generating a predetermined voltage with using the back-up power source; a control device energized from the power source with the predetermined voltage so as to be activated; and a power source control device. The control device determines whether activation is performed for the first time. The control device executes a stand-by process, and then, executes a boot process when the activation is performed for the first time. The control device executes the boot process without executing the stand-by process when the activation is after the first time.

Abstract: An in-vehicle apparatus includes: a flash memory; a memory controller for executing an initialization process; a backup power source; a power source; a controller; and a power source controller. According to incompletion of initialization, the controller executes standby/boot process. According to completion of initialization, the controller executes the boot process. According to reception of data backup instruction, the controller stores data in the memory. The power source controller switches to a trigger standby mode. According to trigger, the power source controller inputs the energization instruction to the power source. According to termination of trigger, the power source controller inputs the data backup instruction to the controller. According to completion of backup, the power source controller halts to input the energization instruction, and switches to the trigger standby mode. According to incompletion of backup, the power source controller resets the switch and the power source.

Abstract: A voltage control system is configured with a constant voltage circuit, a semiconductor package and a power supply package. A power supply chip of the power supply package is configured to control the constant voltage circuit based on an input voltage supplied to the semiconductor package and an operating voltage of a semiconductor device so that the input voltage decreases as the voltage difference between the input voltage and the operating voltage increases.

Abstract: In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.

Abstract: A navigation device for a vehicle includes: a memory device including a NAND type flash memory for storing a predetermined program and a boot program and a controller for searching a failure block in the flash memory and managing a corresponding relation between a logic block and a physical block with eliminating failure blocks; a back-up power source; a power source switch for coupling the memory device with the back-up power source; a power source for generating a predetermined voltage with using the back-up power source; a control device energized from the power source with the predetermined voltage so as to be activated; and a power source control device. The control device determines whether activation is performed for the first time. The control device executes a stand-by process, and then, executes a boot process when the activation is performed for the first time. The control device executes the boot process without executing the stand-by process when the activation is after the first time.

Abstract: The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.

Abstract: A voltage control system is configured with a constant voltage circuit, a semiconductor package and a power supply package. A power supply chip of the power supply package is configured to control the constant voltage circuit based on an input voltage supplied to the semiconductor package and an operating voltage of a semiconductor device so that the input voltage decreases as the voltage difference between the input voltage and the operating voltage increases.

Abstract: A controller 3 of a memory card is a provided with a command decoding circuit 6 for decoding commands issued by a host HT, a command enable register 8 in which the validity or invalidity of the received command, and a command detection signal generating circuit 7 for detecting a valid command on the basis of the result of decoding by the command decoding circuit 6 and a value set by the command enable register 8. If the command enable register 8 receives a validly set command, the command detection signal generating circuit 7 will supply a detection signal to a control unit 4 to execute processing prescribed for each command. the command enable register 8 receives an invalidly set command, no detection signal will be supplied, and the command will be ignored.

Abstract: In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.

Abstract: In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.

Abstract: The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.

Abstract: A risk of data garbling due to cumulative impact of disturbances occurring in memory areas in which no rewrite occurs is to be prevented. A memory device has an erasable and writable nonvolatile memory and a control circuit, wherein the control circuit is enabled to perform processing at a prescribed timing to replace memory areas. The replacement processing is accomplished by writing stored data in a first memory area in which rewriting is relatively infrequent into an unused second memory area, and making the second memory area into which the writing has been done a used area in place of the first memory area. Since this replacement processing is intended to replace memory areas in which rewriting is infrequent with other memory areas as described above, it is possible to prevent the risk of data garbling due to the cumulative impact of disturbances occurring in memory areas in which no rewrite occurs.

Abstract: A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.

Abstract: The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.

Abstract: When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.