Patents by Inventor Motoki Kanamori
Motoki Kanamori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080133860Abstract: Whether an initial command outputted from a host is ‘CMD1’ or ‘CMD55+CMD41’ is detected with an initial command detection portion 8, and the result of detection is set in an SD/MMC register 13. Reset process for hardware and that for firmware are carried out based on the result of detection set in the SD/MMC register 13. Thereafter, a microcomputer 7 sets data indicating in which mode, MultiMedia Card mode or SD mode, the firmware reset process was carried out, in a F/W process SD/MMC register 14. A H/W-F/W mode comparison circuit 15 compares data in the SD/MMC register 13 with data in the F/W process SD/MMC register 14. If these data agree with each other, busy state is released, and command wait state is established. If they disagree with each other, a disagreement occurrence detection signal is outputted to the microcomputer 7, and power-on reset processing is performed again.Type: ApplicationFiled: October 26, 2007Publication date: June 5, 2008Inventors: Motoki Kanamori, Shigeo Kurakata, Chiaki Kumahara, Hidefumi Odate, Atsushi Shikata
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Patent number: 7370168Abstract: The invention intends to provide a memory card conforming to an HS-MMC mode in a standard of a multimedia card, while securing compatibility of both standards of the multimedia card and an SD card. In a normal MMC mode, the data is outputted at a fall edge of a clock signal. A frequency of the clock signal is about 20 MHz. When the data is outputted at the fall edge of the clock signal, data output is in time for a next clock signal. When a parameter ‘1’ is set to a timing register provided in a host interface, the memory card is transitioned into the HS-MMC mode. In the HS-MMC mode, a clock signal frequency is increased to about 52 MHz. Here, the data is outputted at the rise edge of the clock signal, whereby the data output is brought in time for the rise edge of the next clock signal.Type: GrantFiled: March 30, 2004Date of Patent: May 6, 2008Assignee: Renesas Technology Corp.Inventors: Motoki Kanamori, Kunihiro Katayama, Yasuhiro Nakamura, Satoshi Yoshida, Shinsuke Asari
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Patent number: 7343445Abstract: A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition.Type: GrantFiled: October 3, 2006Date of Patent: March 11, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Kunihiro Katayama, Motoki Kanamori, Atsushi Shikata, Hidefumi Oodate, Atsushi Shiraishi
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Publication number: 20080059852Abstract: In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.Type: ApplicationFiled: October 23, 2007Publication date: March 6, 2008Inventors: Hidefumi Oodate, Atsushi Shiraishi, Shigeo Kurakata, Kunihiro Katayama, Motoki Kanamori
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Publication number: 20080046643Abstract: A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.Type: ApplicationFiled: October 12, 2007Publication date: February 21, 2008Inventors: Kenji Kozakai, Yuusuke Jono, Motoki Kanamori, Kazunori Furusawa, Atsushi Shikata, Yosuke Yukawa
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Patent number: 7305589Abstract: In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.Type: GrantFiled: May 8, 2002Date of Patent: December 4, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hidefumi Oodate, Atsushi Shiraishi, Shigeo Kurakata, Kunihiro Katayama, Motoki Kanamori
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Patent number: 7296097Abstract: Whether an initial command outputted from a host is ‘CMD1’ or ‘CMD55+CMD41’ is detected with an initial command detection portion 8, and the result of detection is set in an SD/MMC register 13. Reset process for hardware and that for firmware are carried out based on the result of detection set in the SD/MMC register 13. Thereafter, a microcomputer 7 sets data indicating in which mode, MultiMedia Card mode or SD mode, the firmware reset process was carried out, in a F/W process SD/MMC register 14. A H/W-F/W mode comparison circuit 15 compares data in the SD/MMC register 13 with data in the F/W process SD/MMC register 14. If these data agree with each other, busy state is released, and command wait state is established. If they disagree with each other, a disagreement occurrence detection signal is outputted to the microcomputer 7, and power-on reset processing is performed again.Type: GrantFiled: March 20, 2003Date of Patent: November 13, 2007Assignee: Renesas Technology Corp.Inventors: Motoki Kanamori, Shigeo Kurakata, Chiaki Kumahara, Hidefumi Odate, Atsushi Shikata
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Patent number: 7292480Abstract: A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.Type: GrantFiled: July 18, 2005Date of Patent: November 6, 2007Assignee: Renesas Technology Corp.Inventors: Kenji Kozakai, Yuusuke Jono, Motoki Kanamori, Kazunori Furusawa, Atsushi Shikata, Yosuke Yukawa
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Publication number: 20070233956Abstract: A controller 3 of a memory card is a provided with a command decoding circuit 6 for decoding commands issued by a host HT, a command enable register 8 in which the validity or invalidity of the received command, and a command detection signal generating circuit 7 for detecting a valid command on the basis of the result of decoding by the command decoding circuit 6 and a value set by the command enable register 8. If the command enable register 8 receives a validly set command, the command detection signal generating circuit 7 will supply a detection signal to a control unit 4 to execute processing prescribed for each command. the command enable register 8 receives an invalidly set command, no detection signal will be supplied, and the command will be ignored.Type: ApplicationFiled: May 29, 2007Publication date: October 4, 2007Inventors: Atsushi Shikata, Kunihiro Katayama, Masato Matsumoto, Kazuto Izawa, Motoki Kanamori
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Publication number: 20070186033Abstract: A risk of data garbling due to cumulative impact of disturbances occurring in memory areas in which no rewrite occurs is to be prevented. A memory device has an erasable and writable nonvolatile memory and a control circuit, wherein the control circuit is enabled to perform processing at a prescribed timing to replace memory areas. The replacement processing is accomplished by writing stored data in a first memory area in which rewriting is relatively infrequent into an unused second memory area, and making the second memory area into which the writing has been done a used area in place of the first memory area. Since this replacement processing is intended to replace memory areas in which rewriting is infrequent with other memory areas as described above, it is possible to prevent the risk of data garbling due to the cumulative impact of disturbances occurring in memory areas in which no rewrite occurs.Type: ApplicationFiled: March 19, 2007Publication date: August 9, 2007Inventors: Chiaki Shinagawa, Atsushi Shiraishi, Motoki Kanamori
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Publication number: 20070136616Abstract: A memory card is provided in which power consumption is reduced by the pull-up resistor of an input terminal and a misoperation induced by the pull-down resistor of a host apparatus is prevented. The memory card has a select terminal connected to the pull-up resistor. When the mode of the memory card is determined based on an input from the select terminal, a relatively low resistance value is selected for the pull-up resistor of the select terminal before a determination timing and the pull-up resistor is restored to an initial resistance value after the mode determination. A relatively high resistance value reduces a leakage current consumed by the pull-up resistor of the select terminal. When a pull-down resistor is connected to the terminal of a memory card host to which the memory card is attached, if the resistance value of the pull-up resistor is excessively high, it is influenced by the drawing in of a current by the pull-down resistor.Type: ApplicationFiled: February 8, 2007Publication date: June 14, 2007Inventors: Shigeo Kurakata, Kunihiro Katayama, Motoki Kanamori, Atsushi Shikata, Tetsuya Iida
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Patent number: 7188265Abstract: A memory card is provided in which power consumption is reduced by the pull-up resistor of an input terminal and a misoperation induced by the pull-down resistor of a host apparatus is prevented. The memory card has a select terminal connected to the pull-up resistor. When the mode of the memory card is determined based on an input from the select terminal, a relatively low resistance value is selected for the pull-up resistor of the select terminal before a determination timing and the pull-up resistor is restored to an initial resistance value after the mode determination. A relatively high resistance value reduces a leakage current consumed by the pull-up resistor of the select terminal. When a pull-down resistor is connected to the terminal of a memory card host to which the memory card is attached, if the resistance value of the pull-up resistor is excessively high, it is influenced by the drawing in of a current by the pull-down resistor.Type: GrantFiled: November 20, 2003Date of Patent: March 6, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Shigeo Kurakata, Kunihiro Katayama, Motoki Kanamori, Atsushi Shikata, Tetsuya Iida
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Publication number: 20070033334Abstract: A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition.Type: ApplicationFiled: October 3, 2006Publication date: February 8, 2007Inventors: Kunihiro Katayama, Motoki Kanamori, Atsushi Shikata, Hidefumi Oodate, Atsushi Shiraishi
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Patent number: 7133961Abstract: A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition.Type: GrantFiled: July 16, 2002Date of Patent: November 7, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Kunihiro Katayama, Motoki Kanamori, Atsushi Shikata, Hidefumi Oodate, Atsushi Shiraishi
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Publication number: 20060248388Abstract: Whether an initial command outputted from a host is ‘CMD1’ or ‘CMD55+CMD41’ is detected with an initial command detection portion 8, and the result of detection is set in an SD/MMC register 13. Reset process for hardware and that for firmware are carried out based on the result of detection set in the SD/MMC register 13. Thereafter, a microcomputer 7 sets data indicating in which mode, MultiMedia Card mode or SD mode, the firmware reset process was carried out, in a F/W process SD/MMC register 14. A H/W-F/W mode comparison circuit 15 compares data in the SD/MMC register 13 with data in the F/W process SD/MMC register 14. If these data agree with each other, busy state is released, and command wait state is established. If they disagree with each other, a disagreement occurrence detection signal is outputted to the microcomputer 7, and power-on reset processing is performed again.Type: ApplicationFiled: March 20, 2003Publication date: November 2, 2006Inventors: Motoki Kanamori, Shigeo Kurakata, Chiaki Kumahara, Hidefumi Odate, Atsushi Shikata
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Publication number: 20060233032Abstract: When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.Type: ApplicationFiled: June 16, 2006Publication date: October 19, 2006Inventors: Motoki Kanamori, Kunihiro Katayama, Atsushi Shiraishi, Shigeo Kurakata, Atsushi Shikata
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Patent number: 7116578Abstract: In a card storage device containing a non-volatile memory and a buffer memory, the buffer memory includes a plurality of banks. Data is transferred sequentially from a host CPU to the banks of the buffer memory, data is transferred to the non-volatile memory from a bank that becomes full, a write operation is started when one unit of data to be written into the non-volatile memory at a time has been transferred and, without waiting for the data to be written, the next write data is transferred from the host CPU to a bank from which write data has been transferred.Type: GrantFiled: March 11, 2004Date of Patent: October 3, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Motoki Kanamori, Takayuki Tamura, Kenji Kozakai, Atsushi Shikata, Shinsuke Asari
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Patent number: 7102943Abstract: When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.Type: GrantFiled: June 15, 2005Date of Patent: September 5, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Motoki Kanamori, Kunihiro Katayama, Atsushi Shiraishi, Shigeo Kurakata, Atsushi Shikata
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Patent number: 7061812Abstract: Disclosed is a memory card which ensures high-speed data writing operations. The memory card is formed of an erasable and programmable nonvolatile memory and a control circuit. A memory array of the nonvolatile memory has an erasing table including a first flag designating whether a memory area is a vacant area or not in every erasing unit. The control circuit exercises, when the number of memory areas in which the erasable data is written becomes a constant value, pre-erasing control to previously erase the erasable data over the memory area depending on the first flag indicating a vacant area. Since the erasing process is previously executed to the vacant memory area, necessity for insertion of the erasing process just before the writing process using the vacant memory area can be reduced and thereby writing data to the memory card can be highly speeded.Type: GrantFiled: April 2, 2004Date of Patent: June 13, 2006Assignee: Renesas Technology Corp.Inventors: Chiaki Shinagawa, Motoki Kanamori, Atsushi Shiraishi
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Patent number: 7002853Abstract: A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.Type: GrantFiled: June 24, 2004Date of Patent: February 21, 2006Assignee: Renesas Technology Corp.Inventors: Kenji Kozakai, Yuusuke Jono, Motoki Kanamori, Kazunori Furusawa, Atsushi Shikata, Yosuke Yukawa