Abstract: A circuit for detecting a disturbance signal in an information signal for a read channel circuit includes a resistor connected to ground and a capacitor to form an RC circuit to detect the disturbance. The read channel receives the information signal and the detection signal.

Abstract: A switch (380) couples one group of MR channels (340, 342, 344) while decoupling another group of MR channels (340, 342 and 344). Thus, the parasitic capacitance associated with the decoupled group of MR channels does not limit the frequency response of the preamplifier.

Abstract: A circuit suppresses an additive transient disturbance in an input signal. A main signal path transmits the input signal, and a switchable signal path is switchable into the main signal path during a portion of the disturbance. A positive envelope detector and a negative envelope detector detects, respectively, a positive envelope signal and a negative envelope signal. In response to these signals, positive and negative envelope signals are subtracted from the main signal path only during the portion of the disturbance.

Abstract: Modem comprising a delta modulation (DM) encoder and a DM decoder which has noise-reducing capability in the demodulation of encoded binary pulse signals representative of constant amplitude signals. The DM decoder includes a 1-click delay circuit operable in conjunction with a logic circuit and an integrator to produce a demodulated output signal which is the same as the preceding signal when the input signals to the DM encoder are constant amplitude signals, thereby eliminating are substantially reducing granular noise arising from a constant analog input to the modem without requiring a special filter. The logic circuit of the DM decoder may be an exclusive NOR gate which compares the 1-clock delayed binary pulse signal with the binary pulse signal and provides a control signal output based upon the comparison. The control signal output from the exclusive NOR gate controls the output of the integrator and enables the integrator to produce a substantially noise-free demodulated output signal.

Abstract: A read only memory device with a matrix of series connected FET's addressed with X and Y decoding, a control switch between the output line and a voltage source operant to connect or not the voltage source to the output line in response to a control signal phi, and a second control switch, responsive to the same signal phi, provided between ground and each string of series connected FET's.