Patents by Inventor Motoo Nakano

Motoo Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7366539
    Abstract: A mobile terminal having a function of, while a broadcast channel is established, receiving broadcast through the broadcast channel, includes a memory storing an address or addresses of at least one uniform resource locator (URL) relating to the broadcast channel, as a pair with data of the broadcast channel, a judge unit judging whether an address of a uniform resource locator through which access is made to a web content linking to a currently receiving broadcast channel is stored in the memory, and a controller, when the address is judged to be stored in the memory, making access to the web content through the address.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: April 29, 2008
    Assignee: NEC Corporation
    Inventor: Motoo Nakano
  • Publication number: 20050003840
    Abstract: A mobile terminal having a function of, while a broadcast channel is established, receiving broadcast through the broadcast channel, includes a memory storing an address or addresses of at least one uniform resource locator (URL) relating to the broadcast channel, as a pair with data of the broadcast channel, a judge unit judging whether an address of a uniform resource locator through which access is made to a web content linking to a currently receiving broadcast channel is stored in the memory, and a controller, when the address is judged to be stored in the memory, making access to the web content through the address.
    Type: Application
    Filed: July 2, 2004
    Publication date: January 6, 2005
    Inventor: Motoo Nakano
  • Patent number: 6836668
    Abstract: A portable communication apparatus allowing increased flexibility and convenience is disclosed. A switch is provided to select one of a voice-character conversion communication mode and a character-voice conversion communication mode depending on a setting instruction. A voice-character converter performs a selected one of a first conversion from voice to character data and a second conversion from character to voice data according to the selected communication mode.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: December 28, 2004
    Assignee: NEC Corporation
    Inventor: Motoo Nakano
  • Patent number: 6639941
    Abstract: There is provided a radio-signal transceiver including an antenna, a radio-signal receiver receiving a message having been received through the antenna, addressed to a calling number of the radio-signal transmitter, a main controller controlling an operation of the radio-signal receiver, an interface through which a command is input into the radio-signal receiver, an auxiliary controller analyzing the command and transmitting a signal indicative of an operation represented by the command, to the main controller, a display screen displaying the message, and a message analyzer analyzing the message and extracting data to be registered, the auxiliary controller making judgement as to whether a received message is able to be registered, based on analysis made by the message analyzer, and registering a received message automatically or manually, if a received message is judged to be able to be registered.
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: October 28, 2003
    Assignee: NEC Corporation
    Inventor: Motoo Nakano
  • Patent number: 6251743
    Abstract: Microstructures, including a plurality of spaced structural members which are bendable under an external force, undergo a treating method using a first treating liquid, to prevent permanent deformation, by removing the microstructure from the first treating liquid to an environment having a pressure less than atmospheric pressure; or moving the microstructure from the first treating liquid to a second treating liquid having a smaller surface tension than the first treating liquid, and then removing the microstructure from the second liquid; or drying the microstructure removed from the first treating liquid by exposing same to a liquid vapor having a smaller surface tension than the first treating liquid; or removing the microstructure from the first treating liquid to the atmosphere, and drying the microstructure using an energy beam of high intensity or an ultrasonic wave.
    Type: Grant
    Filed: May 5, 1998
    Date of Patent: June 26, 2001
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Motoo Nakano, Hiroshi Nomura, Masaya Katayama, Toshimi Ikeda, Fumihiko Inoue, Junichi Ishikawa, Masahiro Kuwamura
  • Patent number: 5888633
    Abstract: A micro-structure including at least a first bendable member having first and second ends and being supported at the first end only, and either being spaced from a rigid component, or being spaced from a second bendable member also supported only at a first end thereof. The first member has a length L from the first end to the second end specified by one of the following equations: (a) for the first member adjacent to the rigid component: L<(2Edt.sup.3 /3P).sup.1/4, wherein E is a Young's modulus of a material of the first member; d is a distance of the space between the first member and the rigid component; t is a thickness of the first member; and P is an external pressure applied to the first member; or b) for the first member adjacent to the second member: L<(2Ed't.sup.3 /3P).sup.1/4, wherein E, t and P are as defined above; and d' is a distance of the space between the first and second members.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: March 30, 1999
    Assignee: Fujitsu Limited & Fujitsu VLSI Limited
    Inventors: Motoo Nakano, Hiroshi Nomura, Masaya Katayama, Toshimi Ikeda, Fumihiko Inoue, Junichi Ishikawa, Masahiro Kuwamura
  • Patent number: 5670885
    Abstract: A semiconductor device has a first-conduction-type semiconductor substrate (19), an internal circuit including a vertical bipolar transistor (18) formed in a second-conduction-type semiconductor layer (20), and a protective element (14). The protective element comprises a first-conduction-type diffusion layer (22a) formed at an upper part of a second-conduction-type semiconductor layer (20a) disposed on the semiconductor substrate (19), and a second-conduction-type diffusion layer (27, 30) formed in the first-conduction-type diffusion layer (22a). The diffusion layer (27, 30) is at least partly deeper than an emitter diffusion layer (23) of the vertical bipolar transistor (18).
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: September 23, 1997
    Assignee: Fujitsu Limited
    Inventors: Takashi Iwai, Motoo Nakano
  • Patent number: 5652167
    Abstract: Micro-structures comprising at least a structural member, which is liable to be bent under an external force and formed so as to leave a space between the member and another member liable to be bent and/or other rigid component, are successfully treated using a treating liquid, without suffering permanent deformation resulting from the use of the treating liquid, by removing the micro-structures from the liquid to an environment having a pressure less than the atmospheric pressure; or displacing the micro-structures from the treating liquid to another treating liquid having a smaller surface tension than that of the former liquid, and then removing the micro-structures from the latter liquid; or drying the micro-structures removed from the treating liquid by exposing the same to vapor of a liquid having a smaller surface tension than that of the treating liquid; or removing the micro-structures from the treating liquid to the atmosphere, and drying them using an energy beam of high intensity or an ultrasonic
    Type: Grant
    Filed: June 29, 1993
    Date of Patent: July 29, 1997
    Assignees: Fujitsu Ltd., Fujitsu VLSI Ltd.
    Inventors: Motoo Nakano, Hiroshi Nomura, Masaya Katayama, Toshimi Ikeda, Fumihiko Inoue, Junichi Ishikawa, Masahiro Kuwamura
  • Patent number: 5648676
    Abstract: A semiconductor device has a first-conduction-type semiconductor substrate (19), an internal circuit including a vertical bipolar transistor (18) formed in a second-conduction-type semiconductor layer (20), and a protective element (14). The protective element comprises a first-conduction-type diffusion layer (22a) formed at an upper part of a second-conduction-type semiconductor layer (20a) disposed on the semiconductor substrate (19), and a second-conduction-type diffusion layer (27, 30) formed in the first-conduction-type diffusion layer (22a). The diffusion layer (27, 30) is at least partly deeper than an emitter diffusion layer (23) of the vertical bipolar transistor (18).
    Type: Grant
    Filed: January 23, 1996
    Date of Patent: July 15, 1997
    Assignee: Fujitsu Limited
    Inventors: Takashi Iwai, Motoo Nakano
  • Patent number: 5427977
    Abstract: An Si or SiC semiconductor layer is subjected to anodic oxidation in an HF solution to form a porous semiconductor layer. Without drying, the porous semiconductor layer is then immersed in pure water. Ultrasonic waves applied to the pure water shorten the reaction time and help bubbles separate from the surface of the porous region. The porous semiconductor layer is used for forming a pn junction, and carriers are injected into the pn junction.
    Type: Grant
    Filed: January 6, 1994
    Date of Patent: June 27, 1995
    Assignee: Fujitsu Limited
    Inventors: Masao Yamada, Motoo Nakano, George J. Collins, Tetsuro Tamura, Akira Takazawa
  • Patent number: 5331180
    Abstract: An Si or SiC semiconductor layer is subjected to anodic oxidization in an HF solution to form a porous semiconductor layer. Without drying the porous semiconductor layer, it is then dipped in pure water. Ultrasonic waves applied to the pure water shorten the reaction time and help bubbles separate from the surface of the porous region. The porous semiconductor layer is used for forming a pn junction, and carriers are injected into the pn junction.
    Type: Grant
    Filed: April 28, 1993
    Date of Patent: July 19, 1994
    Assignee: Fujitsu Limited
    Inventors: Masao Yamada, Motoo Nakano, George J. Collins, Tetsuro Tamura, Akira Takazawa
  • Patent number: 5250465
    Abstract: A semiconductor device having small diameter via-holes, particularly not greater than 0.6 microns, for a multilayer interconnection is produced by a method comprising covering an interlayer film and via-holes with a continuous, first metal film by a CVD process, and heating and melting by an irradiation of an energy beam a second metal film deposited on the first film by a PVD process, together with the first metal film, to fully fill the via-holes with the material from the outside of the holes, to thus form conductive plugs therein. The deposition of the material of the second metal film and the filling of the via-holes may be simultaneously performed by a high temperature sputtering process.
    Type: Grant
    Filed: January 24, 1992
    Date of Patent: October 5, 1993
    Assignee: Fujitsu Limited
    Inventors: Masako Iizuka, Ryoichi Mukai, Motoo Nakano
  • Patent number: 4841349
    Abstract: A semiconductor photodetector device comprises an insulating gate field effect transistor having a gate in which a PN junction (J) is formed on an insulating layer. The gate is formed of a gate electrode (14) of P.sup.+ -type single crystalline silicon and a gate extension portion (17) of N.sup.+ -type single crystalline silicon. Electric charges generated by a light falling on an area including the PN junction are accummulated in the gate electrode (14). A signal of the accumulated electric charge is amplified by the transistor to obtain an output signal (V.sub.out) for detection.
    Type: Grant
    Filed: October 28, 1987
    Date of Patent: June 20, 1989
    Assignee: Fujitsu Limited
    Inventor: Motoo Nakano
  • Patent number: 4806769
    Abstract: An improved disk exchangeable target mechanism for an ion implantation system includes an effective cooling means for preventing thermal damage to a resist and for improving an implantation quality of semiconductor wafers. The target mechanism includes a metal disk on which a semiconductor wafer(s) to be ion-implanted are mounted on a first face thereof, a support including a metal base having the target disk mounted thereon, and a shaft incorporated with the base, and a medium, provided between a second face of the target disk opposite to the first face and the base, for thermally contact therebetween. Preferably, the base of the support is provided with a cavity and the shaft is provided with holes communicating with the cavity, whereby a cooling medium is inserted into the cavity through one hole and is drained from the cavity through another hole.
    Type: Grant
    Filed: May 19, 1987
    Date of Patent: February 21, 1989
    Assignee: Fujitsu Limited
    Inventors: Haruhisa Mori, Motoo Nakano
  • Patent number: 4788473
    Abstract: A plasma generating device comprises:a rectangular wave guide for transmitting microwaves, wherein the width of the plasma generating device is decreased in the direction of an electrical field of the microwaves; a plasma generating chamber wherein plasma is generated by absorbing, in a gas, microwave energy transmitted by the rectangular wave guide, and a part of the plasma generating chamber has a rectangular cross-section taken along the plane perpendicular to the microwave propagation direction. A magnetic field generating device is provided having the same axial direction as the direction of propagation of the microwaves and applies a magnetic field having an Electron Cyclotron Resonance intensity to the plasma generating chamber.
    Type: Grant
    Filed: June 19, 1987
    Date of Patent: November 29, 1988
    Assignee: Fujitsu Limited
    Inventors: Haruhisa Mori, Motoo Nakano, Yoshinobu Ono, Takashi Igarashi, Masanao Hotta
  • Patent number: 4727043
    Abstract: An improved electrically alterable read-only memory (EAROM) is offered by the method of the invention, the memory device comprising a floating gate type field effect transistor in which a part of the floating gate and a part of the drain region formed in a silicon substrate overlap. According to the method, impurity atoms are ion implanted into a part of a region where the drain region is to be formed through an insulation layer of silicon dioxide on the region. Thereafter, the insulation layer through which ion implantation was carried out is removed and a fresh insulation layer of silicon dioxide is formed where the old insulation layer was removed. By this method, a good, thin insulation film is fabricated. By virtue of the fresh insulation layer devoid of trap centers which trap electric charges, the insulation layer is free from defects that interrupt flow of electrons required for writing or erasing of information.
    Type: Grant
    Filed: October 29, 1985
    Date of Patent: February 23, 1988
    Assignee: Fujitsu Limited
    Inventors: Takashi Matsumoto, Motoo Nakano
  • Patent number: 4669062
    Abstract: A dynamic random access memory (DRAM) cell has three MIS transistors arranged in a two-tiered structure with high packing density. A read select MIS transistor has source, drain and channel regions formed in the substrate and is covered by a first insulating layer and a semiconductor layer. A write select MIS transistor has source and drain regions formed in the semiconducting layer, the first insulating layer having a contact window therein through which the drain regions of the write select and read select MIS transistors are connected.
    Type: Grant
    Filed: September 20, 1985
    Date of Patent: May 26, 1987
    Assignee: Fujitsu Limited
    Inventor: Motoo Nakano
  • Patent number: 4541074
    Abstract: A ROM including memory cells having characteristics corresponding to the "1" or "0" information to be stored, the correspondence to "1" or "0" information being achieved by changing the conductivity type of at least a portion of a semiconductor layer in the semiconductor devices of the memory cells.
    Type: Grant
    Filed: June 28, 1982
    Date of Patent: September 10, 1985
    Assignee: Fujitsu Limited
    Inventor: Motoo Nakano
  • Patent number: 4538166
    Abstract: A 1-transistor and 1-capacitor type memory cell includes a first capacitor electrode and a field shield electrode which serves as the second capacitor electrode of the memory cell. A high impurity concentration layer is formed just beneath the first electrode of the capacitor of the memory cell and extends to a field region to form a channel stop area. However, the high impurity concentration layer is inhibited from extending to the transistor gate. This arrangement provides so-called 1-transistor and 1-capacitor type memory cells which are highly integrated, have a long persisting time and are resistant to alpha rays.
    Type: Grant
    Filed: January 17, 1984
    Date of Patent: August 27, 1985
    Assignee: Fujitsu Limited
    Inventor: Motoo Nakano
  • Patent number: 4503315
    Abstract: A semiconductor device with a fuse including an insulating layer having at least one step. A fusible film on the insulating layer crosses the step and a covering film is formed on the fusible film, the step and the insulating layer. When the portion of the fusible film crossing the step is irradiated with a laser beam the portion of the fusible film on the upper surface of the insulating layer melts and flows onto the lower surface of the insulating layer without forming a hole, thereby separating the fusible film at the step.
    Type: Grant
    Filed: December 27, 1982
    Date of Patent: March 5, 1985
    Assignee: Fujitsu Limited
    Inventors: Hajime Kamioka, Mikio Takagi, Noriaki Sato, Motoo Nakano, Takashi Iwai