Abstract: A 1-transistor and 1-capacitor type memory cell includes a first capacitor electrode and a field shield electrode which serves as the second capacitor electrode of the memory cell. A high impurity concentration layer is formed just beneath the first electrode of the capacitor of the memory cell and extends to a field region to form a channel stop area. However, the high impurity concentration layer is inhibited from extending to the transistor gate. This arrangement provides so-called 1-transistor and 1-capacitor type memory cells which are highly integrated, have a long persisting time and are resistant to alpha rays.

Abstract: A semiconductor device with a fuse including an insulating layer having at least one step. A fusible film on the insulating layer crosses the step and a covering film is formed on the fusible film, the step and the insulating layer. When the portion of the fusible film crossing the step is irradiated with a laser beam the portion of the fusible film on the upper surface of the insulating layer melts and flows onto the lower surface of the insulating layer without forming a hole, thereby separating the fusible film at the step.

Abstract: Disclosed here is an IGFET formed on the single crystal silicon substrate where the major plane surface is deviated within the range from 22 degree to 34 degree toward the crystallographic surface {1,1,1} from {1,0,0} or on the silicon epitaxial layer formed on said substrate. Here, generation of silicon nitride is suppressed, which is newly formed under the mask in the selective oxidation process using the silicon nitride as the mask and also is the main cause of lowering the breakdown voltage of the gate insulating film. In addition, various kinds of functional characteristics depending on the crystallographic surface orientation are not interfered at all. Thereby, the present invention can offer an IGFET which drastically improved the breakdown voltage failure rate of the gate insulating film while keeping the functional characteristics at the best condition.

Abstract: Disclosed here is an IGFET formed on the single crystal silicon substrate where the major plane surface is deviated within the range from 22 degree to 34 degree toward the crystallographic surface {1,1,1,} from {1,0,0} or on the silicon epitaxial layer formed on said substrate. Here, generation of silicon nitride is suppressed, which is newly formed under the mask in the selective oxidation process using the silicon nitride as the mask and also is the main cause of lowering the breakdown voltage of the gate insulating film. In addition, various kinds of functional characteristics depending on the crystallographic surface orientation are not interfered at all. Thereby, the present invention can offer an IGFET which drastically improved the breakdown voltage failure rate of the gate insulating film while keeping the functional characteristics at the best condition.

Abstract: The method of manufacture of a semiconductor device having wirings or electrodes of silicide formed by: exposing parts of a single-crystal silicon layer formed on an insulating substrate, forming a film of metal over the exposed parts, and annealing so that a silicide is formed of the silicon and metal throughout the entire thickness of the silicon layer. The single-crystal silicon layer may be formed on a sapphire or spinel substrate having a film of silicon dioxide, sapphire or spinel, epitaxially grown on a silicon substrate.

Abstract: A method of producing a semiconductor device which comprises steps of forming an insulator layer on a semiconductor substrate, forming a semiconductor layer on the insulator layer and then annealing the semiconductor layer by means of a first laser with a second laser being applied to the insulator layer to heat it while the first layer is applied to the semiconductor laser.

Abstract: The invention is concerned with an improved method of producing a one-transistor cell for a dynamic RAM having a capacitor plate, a transfer gate and a shallow n.sup.+ -type region and a deeper p.sup.+ -type region for a junction capacitance. After formation of a thin oxide layer of a dielectric for an MOS capacitance, a patterned photo resist layer is formed. Using the photo resist layer as a mask, n-type impurities are doped into a semiconductor substrate. The capacitor plate and a masking layer are deposited on the photo resist layer and the thin oxide layer. P-type impurities are doped into the capacitor plate. Then, portions of the capacitor plate and masking layer on the photo resist layer are removed by removing the photo resist layer. An end portion of the capacitor plate is removed from under an edge of the remaining masking layer by etching. The p-type impurities are diffused into the silicon substrate by heating to form the deeper p.sup.+ -type region which does not extend beyond the n.sup.

Abstract: A method of manufacturing SOS type semiconductor devices having small leakage current comprising the steps of forming a single crystal semiconductor film on an insulator single crystal substrate, selectively forming a film for masking against oxidation on the surface of the single crystal semiconductor film, and thermally oxidizing the single crystal semiconductor film, in a region which is not covered with the masking film, down to the surface of the insulating single crystal substrate in a water vapor atmosphere having a high pressure which is at least more than atmospheric pressure.

Abstract: A semiconductor memory device provides a plurality of bit lines, a plurality of memory cells each of which is connected to a pair of different bit lines, a plurality of common word wires each of which is connected to the memory cells via a transmission gate. A characteristic feature of the present invention is to provide at least one amplifier between two memory cells which are connected to a word line or a bit line so as to prevent an increase of the access time of the memory device.

Abstract: In the production of a semiconductor device, such as an IC including MOS transistors, impurity ions are implanted into the semiconductor substrate of the device provided with an insulating film. The insulating film is electrically charged by the impurity ions and may be destroyed due to an electric potential between the insulating film and the semiconductor substrate. A novel process provided by the invention prevents the destruction of the insulating film and shortens the ion implantation time, since the beam current of the impurity ions is successively increased until the required dosing amount is obtained.