Patents by Inventor Motoo Nishihara

Motoo Nishihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8369331
    Abstract: A layer 1 network frame is disclosed that includes data of a layer 2 frame. A header of the layer 1 frame header includes: a packet length field to indicate a size of a payload portion of the layer 1 frame, a priority field to indicate a priority of the layer 1 frame, a protocol field to identify a protocol of the data in the layer 2 frame, a frame mode field to indicate a correspondence between the layer 1 frame and the layer 2 frame included within the payload, a stuff field to indicate whether stuff data is contained in the layer 1 frame, and a cyclic redundancy check (CRC) field to indicate a CRC result.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: February 5, 2013
    Assignee: Juniper Networks, Inc.
    Inventor: Motoo Nishihara
  • Patent number: 8045559
    Abstract: A datagram relaying apparatus includes a plurality of protocol terminating units, and a destination determining processor. The destination determining processor includes a path selecting section which determines a transfer destination route for a stream of packets received from any of the protocol terminating units. The path selecting section determines whether or not transfer of the received stream of packets to the transfer destination route is in an inhibition state, and selects another transfer destination route when the transfer of the packet to the transfer destination route is in the inhibition state.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: October 25, 2011
    Assignee: Juniper Networks, Inc.
    Inventors: Kenshin Yamada, Yasuhiro Miyao, Motoo Nishihara
  • Publication number: 20100020803
    Abstract: A layer 1 network frame is disclosed that includes data of a layer 2 frame. A header of the layer 1 frame header includes: a packet length field to indicate a size of a payload portion of the layer 1 frame, a priority field to indicate a priority of the layer 1 frame, a protocol field to identify a protocol of the data in the layer 2 frame, a frame mode field to indicate a correspondence between the layer 1 frame and the layer 2 frame included within the payload, a stuff field to indicate whether stuff data is contained in the layer 1 frame, and a cyclic redundancy check (CRC) field to indicate a CRC result.
    Type: Application
    Filed: August 18, 2009
    Publication date: January 28, 2010
    Applicant: JUNIPER NETWORKS, INC.
    Inventor: Motoo NISHIHARA
  • Publication number: 20090257349
    Abstract: A datagram relaying apparatus includes a plurality of protocol terminating units, and a destination determining processor. The destination determining processor includes a path selecting section which determines a transfer destination route for a stream of packets received from any of the protocol terminating units. The path selecting section determines whether or not transfer of the received stream of packets to the transfer destination route is in an inhibition state, and selects another transfer destination route when the transfer of the packet to the transfer destination route is in the inhibition state.
    Type: Application
    Filed: June 12, 2009
    Publication date: October 15, 2009
    Applicant: JUNIPER NETWORKS, INC.
    Inventors: Kenshin YAMADA, Yasuhiro MIYAO, Motoo NISHIHARA
  • Patent number: 7593399
    Abstract: A layer 1 network frame is disclosed that includes data of a layer 2 frame. A header of the layer 1 frame header includes: a packet length field to indicate a size of a payload portion of the layer 1 frame, a priority field to indicate a priority of the layer 1 frame, a protocol field to identify a protocol of the data in the layer 2 frame, a frame mode field to indicate a correspondence between the layer 1 frame and the layer 2 frame included within the payload, a stuff field to indicate whether stuff data is contained in the layer 1 frame, and a cyclic redundancy check (CRC) field to indicate a CRC result.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: September 22, 2009
    Assignee: Juniper Networks, Inc.
    Inventor: Motoo Nishihara
  • Publication number: 20090234960
    Abstract: A protocol processing apparatus includes: a tag extracting section configured to output a tag data and an input data based on the input data and a protocol data of the input data; a format sheet configured to store a format data common to protocols; and a processing unit configured to refer to said format sheet to execute processes to the tag data and the input data based on the format data, and to output an execution result, and an output data. The tag data is defined for every type of protocol and is managed in a common format to protocols of a plurality of layers.
    Type: Application
    Filed: March 11, 2009
    Publication date: September 17, 2009
    Inventors: Satoshi Kamiya, Hiroshi Ueno, Kiyohisa Ichino, Motoo Nishihara
  • Patent number: 7564844
    Abstract: A datagram relaying apparatus includes a plurality of protocol terminating units, and a destination determining processor. The destination determining processor includes a path selecting section which determines a transfer destination route for a stream of packets received from any of the protocol terminating units. The path selecting section determines whether or not transfer of the received stream of packets to the transfer destination route is in an inhibition state, and selects another transfer destination route when the transfer of the packet to the transfer destination route is in the inhibition state.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: July 21, 2009
    Assignee: Juniper Networks, Inc.
    Inventors: Kenshin Yamada, Yasuhiro Miyao, Motoo Nishihara
  • Patent number: 7324511
    Abstract: In between network devices interconnected by plural optical channels, logical paths are defined according to upper traffic and also priority of the traffic. The network device includes: a frame forming section for reading user packets out of a buffer section composed of plural buffers defined for the respective paths on transfer schedule, and forming path frames having a specified frame length and individual ordinal numbers with respect to each path; a switch for selecting output channels to equally distribute the path frames by round robin scheduling; and data transmitting part for transmitting data on the logical paths. Thus, it is made possible to realize a frame transfer system capable of performing data transmission, which satisfies QOS (Quality Of Service) required for user traffic, on the WDM networks connected by plural OCHs.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: January 29, 2008
    Assignee: NEC Corporation
    Inventor: Motoo Nishihara
  • Patent number: 7298694
    Abstract: To allow performance monitoring of the end-to-end path from the Ingress node to the Egress node of the GFP network by an FCS (Frame Check Sequence) check in a GFP (Generic Frame Procedure) frame, the FCS generation target area is set in the payload field of the GFP frame, no FCS recalculation is performed at the relay node and the GFP frame is transferred to the next node with the FCS added when the GFP frame is received even if an error is detected by the FCS check.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: November 20, 2007
    Assignee: NEC Corporation
    Inventors: Satoshi Kamiya, Motoo Nishihara, Ryuichi Ikematsu
  • Patent number: 7126950
    Abstract: A storage circuit defines a first field for storing first header bits of a first payload signal of a first data unit, a second field, and a third field for storing the first payload signal. The first header bits are equal in number to second header bits of a second payload signal of a second data unit. A division circuit divides the first header bits by a generator polynomial to produce a first error check code. The same generator polynomial is used to divide the second header bits to produce a second error check code. A remainder of division of hypothetical header bits by the generator polynomial is summed to the first error check code to produce a sum which is inserted into the second field of the storage circuit. The hypothetical header bits are greater in number than a total number of bits in the first and second fields, so that the first and second data units can be distinguished from each other by different error check results of the first and second data units.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: October 24, 2006
    Assignee: NEC Corporation
    Inventors: Kazuo Takagi, Naoya Henmi, Shinobu Sasaki, Kurenai Murakami, Motoo Nishihara, Yoshinori Rokugou
  • Publication number: 20060193325
    Abstract: A storage circuit defines a first field for storing first header bits of a first payload signal of a first data unit, a second field, and a third field for storing the first payload signal. The first header bits are equal in number to second header bits of a second payload signal of a second data unit. A division circuit divides the first header bits by a generator polynomial to produce a first error check code. The same generator polynomial is used to divide the second header bits to produce a second error check code. A remainder of division of hypothetical header bits by the generator polynomial is summed to the first error check code to produce a sum which is inserted into the second field of the storage circuit. The hypothetical header bits are greater in number than a total number of bits in the first and second fields, so that the first and second data units can be distinguished from each other by different error check results of the first and second data units.
    Type: Application
    Filed: May 1, 2006
    Publication date: August 31, 2006
    Applicant: NEC Corporation
    Inventors: Kazuo Takagi, Naoya Henmi, Shinobu Sasaki, Kurenai Murakami, Motoo Nishihara, Yoshinori Rokugou
  • Publication number: 20060120365
    Abstract: A layer 1 frame, capable of accommodating data of any protocol selected from an STM (Synchronous Transfer Mode) signal, ATM (Asynchronous Transfer Mode) cells, a primary IP (Internet Protocol) packet and a best effort IP packet in a common frame format, is constructed by an edge node and transmitted to a data transfer system composed of edge nodes, core nodes, etc. The layer 1 frame includes a layer 1 frame header, a layer 1 frame payload and a payload CRC (Cyclic Redundancy Check) field. The layer 1 frame header includes a “Packet Length” identifier, a “Priority” identifier, a “Protocol” identifier indicating the type of the data, a “Frame Mode” identifier, a “Stuff” identifier indicating whether or not stuff data is contained in the layer 1 frame, and a “Header CRC” identifier. The layer 1 frame payload contains a layer 2 frame having a layer 2 frame header and a layer 2 frame payload in which the data is packed.
    Type: Application
    Filed: January 6, 2006
    Publication date: June 8, 2006
    Inventor: Motoo Nishihara
  • Patent number: 7050455
    Abstract: A layer 1 frame, capable of accommodating data of any protocol selected from an STM (Synchronous Transfer Mode) signal, ATM (Asynchronous Transfer Mode) cells, a primary IP (Internet Protocol) packet and a best effort IP packet in a common frame format, is constructed by an edge node and transmitted to a data transfer system composed of edge nodes, core nodes, etc. The layer 1 frame includes a layer 1 frame header, a layer 1 frame payload and a payload CRC (Cyclic Redundancy Check) field. The layer 1 frame header includes a “Packet Length” identifier, a “Priority” identifier, a “Protocol” identifier indicating the type of the data, a “Frame Mode” identifier, a “Stuff” identifier indicating whether or not stuff data is contained in the layer 1 frame, and a “Header CRC” identifier. The layer 1 frame payload contains a layer 2 frame having a layer 2 frame header and a layer 2 frame payload in which the data is packed.
    Type: Grant
    Filed: December 12, 2000
    Date of Patent: May 23, 2006
    Assignee: Juniper Networks, Inc.
    Inventor: Motoo Nishihara
  • Publication number: 20060018321
    Abstract: A datagram relaying apparatus includes a plurality of protocol terminating units, and a destination determining processor. The destination determining processor includes a path selecting section which determines a transfer destination route for a stream of packets received from any of the protocol terminating units. The path selecting section determines whether or not transfer of the received stream of packets to the transfer destination route is in an inhibition state, and selects another transfer destination route when the transfer of the packet to the transfer destination route is in the inhibition state.
    Type: Application
    Filed: July 20, 2005
    Publication date: January 26, 2006
    Inventors: Kenshin Yamada, Yasuhiro Miyao, Motoo Nishihara
  • Patent number: 6976256
    Abstract: A pipeline processing type shaping apparatus and method in which strict shaping processing can also be implemented for a connection at various speed by adding a simplified circuit configuration. A cache portion is provided that links with the processing of a pipeline processing portion, and this cache portion manages flow information of a packet that is being processed in the pipeline processing portion. When there is a packet that belongs to the same flow, the cache portion transfers a parameter to the pipeline processing portion assuming a virtual packet in which relevant packets are all connected. The pipeline processing portion executes pipeline processing based on this virtual parameter. Consequently, also for a flow at an optional peak-rate speed (reciprocal of the input packet interval that belongs to the same flow) and in any high-speed transmission path interface, a predetermined scheduling time by shaping can always be calculated in real time.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: December 13, 2005
    Assignee: NEC Corporation
    Inventor: Motoo Nishihara
  • Patent number: 6970478
    Abstract: In a packet transfer method, a packet to be transferred to a destination access network is generated and transmitted to a transmission-source packet transfer apparatus connected to the transmission-source access network. The packet is converted into a superpacket having a length n times (n is an integer of 2 or more) larger than a fixed-length cell as a switching unit of a relay apparatus arranged on a network serving as a backbone, and sent to the network. The superpacket is relayed using the relay apparatus and transferred to a destination packet transfer apparatus connected to the destination access network. The packet generated by the transmission-source access network is reassembled on the basis of the superpacket transferred from the network, and sent to the destination access network. A packet transfer apparatus and packet communication system are also disclosed.
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: November 29, 2005
    Assignee: NEC Corporation
    Inventor: Motoo Nishihara
  • Patent number: 6947427
    Abstract: A transmission method and a network system can accommodate STM, ATM and IP in a single network by newly proposing a frame network to be used in common in physical layer and data link layer. The transmission method includes transmitting a plurality of packets in multiplexing manner, which header in each packet includes a first field holding a signal indicative of a packet length, a second field holding a signal indicative of a preferential order upon transferring the packet, a third field holding a signal indicative of a kind of traffic, a fourth field holding a signal indicative of a header length, a fifth field holding a control signal depending upon the kind of traffic, and a sixth field holding a signal indicative of a result of CRC operation of the header, a payload holding information signal depending upon kind of the traffic and a signal indicative of a result of CRC operation of the payload.
    Type: Grant
    Filed: September 26, 2000
    Date of Patent: September 20, 2005
    Assignee: NEC Corporation
    Inventors: Yoshinori Rokugo, Motoo Nishihara, Kazuo Takagi
  • Patent number: 6940853
    Abstract: A datagram relaying apparatus includes a plurality of protocol terminating units, and a destination determining processor. The destination determining processor includes a path selecting section which determines a transfer destination route for a stream of packets received from any of the protocol terminating units. The path selecting section determines whether or not transfer of the received stream of packets to the transfer destination route is in an inhibition state, and selects another transfer destination route when the transfer of the packet to the transfer destination route is in the inhibition state.
    Type: Grant
    Filed: January 3, 2001
    Date of Patent: September 6, 2005
    Assignee: Juniper Networks, Inc.
    Inventors: Kenshin Yamada, Yasuhiro Miyao, Motoo Nishihara
  • Patent number: 6754215
    Abstract: In the packet scheduling device, the output class selection part is made to conduct the selective output of priority class, based on the weight count value calculated from a weight value corresponding to minimum guarantee bandwidth for each priority class and the amount of packet accumulated in each queue. The output class selection part operates so that if the weight count value is “0” or more, then the packet length of variable-length packet data to be output is subtracted from the current weight count value to give a renewed weight count value. On the other hand, if the weight count value is less than “0”, until reaching a predetermined repeat count (Cmax−1), the weight value of each priority class is added to the weight count value of all priority classes, and, when reaching the repeat count (Cmax−1), the weight value is added to the weight count value of all priority classes or replaced by half the weight value.
    Type: Grant
    Filed: August 15, 2000
    Date of Patent: June 22, 2004
    Assignee: NEC Corporation
    Inventors: Toshiaki Arikawa, Motoo Nishihara, Michio Masuda
  • Patent number: 6738352
    Abstract: A transfer destination determining apparatus and method performing a load distribution in a network, where a plurality of transfer destination subjects are present as a transfer destination of a datagram, while the same collected flows are transferred to the same transfer destinations, the transfer destinations are allocated with respect to each of the collected flows. This apparatus has an extracting part extracting address and flow discrimination information, in the IP datagram; route solving part determining a transfer path based on the address information. When the determined path is a single path, the transfer destination is uniquely determined and the path is outputted to a post-staged apparatus, whereas when the path is a multi-path having a plurality of transfer destination subjects a multi-path number is outputted to a flow managing means which determines a transfer path corresponding, to a collected flow based on the received flow discrimination information and the multi-path number.
    Type: Grant
    Filed: February 24, 2000
    Date of Patent: May 18, 2004
    Assignee: NEC Corporation
    Inventors: Kenshin Yamada, Michio Masuda, Motoo Nishihara