Patents by Inventor Motoo Nishihara
Motoo Nishihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6678474Abstract: A lightwave network data communications system having such an architecture that routing operation within a lightwave network is simplified, and a high-speed transfer process is attained in a large-scale basic network utilizing a wavelength division multiplexing (WDM) technology which accommodates internet traffics from a plurality of subscriber networks.Type: GrantFiled: March 23, 2000Date of Patent: January 13, 2004Assignee: NEC CorporationInventors: Michio Masuda, Motoo Nishihara, Kenshin Yamada
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Patent number: 6580714Abstract: An ATM switching system includes a plurality of (m) small-scale n×n ATM switch modules, and a coupling module for coupling the ATM switch modules to one another to implement a large-scale ATM switching system. The coupling module includes m concentrators corresponding to the m ATM switch modules. Each concentrator has a multiplexing block for multiplexing m×n signal sequences into n signal sequences, concentration buffer block including a n×n banyan network for specifying one of ATM switch modules for each effective cell based on a destination signal and a plurality of buffers. The concentrator operates at slow transfer rate in a large-scale ATM system so that the performance of the concentrator does not restrict the scale of the ATM system.Type: GrantFiled: November 2, 1998Date of Patent: June 17, 2003Assignee: NEC CorporationInventors: Hideki Nishizaki, Motoo Nishihara
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Patent number: 6546422Abstract: A caching method for caching network contents of a packet transfer network including a packet relay for relaying accesses of clients to servers supplying contents, and a network contents cache device are disclosed. Accesses from the clients to the servers are monitored by the said packet relay to determine a cache priority on the basis of a product of relaying path lengths from the packet relay to the server and frequency of access from the client to the servers and the network contents cache device preferentially caches a response to the access to the server having higher cache priority.Type: GrantFiled: July 1, 1999Date of Patent: April 8, 2003Assignee: NEC CorporationInventors: Kazuhiko Isoyama, Akira Arutaki, Motoo Nishihara
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Patent number: 6512616Abstract: An optical packet switch uses electric circuits to implement input and output sections of an optical switch that performs packet switching. Retiming of packet data in the output section is facilitated to reduce the scale of the circuitry. In the input section a packet-data signal and a clock signal for retiming the packet data are wavelength multiplexed by a wavelength multiplexer and transferred over the same optical waveguide of the optical switch. In the output section the packet-data signal and the clock signal, which have been transferred from the same optical waveguide in the packet switch, are demultiplexed by a wavelength demultiplexer, and retiming of the packet-data signal is performed by an intra-device frame terminating unit.Type: GrantFiled: November 23, 1999Date of Patent: January 28, 2003Assignee: NEC CorporationInventor: Motoo Nishihara
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Patent number: 6452908Abstract: A communication control apparatus includes an input and output unit responsive to reception of a packet, for generating a search request and a destination address of the packet to receive a resultant route data, and for transmitting the packet based on the resultant route data. A memory stores a route tree table having a tree structure of a plurality of nodes, each of which has a node data. A route searching circuit refers to the route tree table in response to the search request to determine a route data of a final node data as the resultant route data from the destination address, and outputs the resultant route to the input and output unit.Type: GrantFiled: December 21, 1998Date of Patent: September 17, 2002Assignee: NEC CorporationInventors: Kenshin Yamada, Motoo Nishihara
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Patent number: 6424620Abstract: A congestion control system comprises an average flowing speed measuring unit for measuring average flowing speed of a transfer packet, a congestion detecting unit for detecting congestion caused by outside blocking based on the average flowing speed, a permissible flowing speed calculating unit for calculating permissible flowing speed of a transfer packet, a flowing speed control unit for controlling the average flowing speed of an entering packet under the permissible flowing speed when detecting congestion, an inside node congestion detecting unit for detecting inside node congestion, a congestion detecting unit for detecting congestion caused by inside blocking from the detection result of the inside node congestion and the congestion caused by the outside blocking, a transfer channel database for storing transfer channel information indicating transfer channels, a transfer channel retrieval unit for retrieving a transfer channel possible to avoid a relay node having the inside node congestion detected wType: GrantFiled: September 21, 1998Date of Patent: July 23, 2002Assignee: NEC CorporationInventor: Motoo Nishihara
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Publication number: 20020090007Abstract: To allow performance monitoring of the end-to-end path from the Ingress node to the Egress node of the GFP network by an FCS (Frame Check Sequence) check in a GFP (Generic Frame Procedure) frame, the FCS generation target area is set in the payload field of the GFP frame, no FCS recalculation is performed at the relay node and the GFP frame is transferred to the next node with the FCS added when the GFP frame is received even if an error is detected by the FCS check.Type: ApplicationFiled: December 20, 2001Publication date: July 11, 2002Inventors: Satoshi Kamiya, Motoo Nishihara, Ryuichi Ikematsu
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Publication number: 20020083190Abstract: The GFP frame transfer apparatus according to the present invention includes a GFP path frame formation unit (7, 8, 11, 13) that stores a label corresponding to a path ID defined to uniquely specify a path from the Ingress node to Egress node within a GFP network in a predetermined field of the extension header area of the GFP frame, stores packets to be transferred through the path in the payload field of the GFP frame and forms a GFP path frame.Type: ApplicationFiled: December 21, 2001Publication date: June 27, 2002Inventors: Satoshi Kamiya, Motoo Nishihara
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Publication number: 20020018468Abstract: In between network devices interconnected by plural optical channels, logical paths are defined according to upper traffic and also priority of the traffic. The network device comprises: a frame forming section for reading user packets out of a buffer section composed of plural buffers defined for the respective paths on transfer schedule, and forming path frames having a specified frame length and individual ordinal numbers with respect to each path; a switch for selecting output channels to equally distribute the path frames by round robin scheduling; and data transmitting means for transmitting data on the logical paths. Thus, it is made possible to realize a frame transfer system capable of performing data transmission, which satisfies QOS (Quality Of Service) required for user traffic, on the WDM networks connected by plural OCHs.Type: ApplicationFiled: August 10, 2001Publication date: February 14, 2002Applicant: NEC CorporationInventor: Motoo Nishihara
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Publication number: 20020016852Abstract: A layer 1 frame, capable of accommodating data of any protocol selected from an STM (Synchronous Transfer Mode) signal, ATM (Asynchronous Transfer Mode) cells, a primary IP (Internet Protocol) packet and a best effort IP packet in a common frame format, is constructed by an edge node and transmitted to a data transfer system composed of edge nodes, core nodes, etc. The layer 1 frame includes a layer 1 frame header, a layer 1 frame payload and a payload CRC (Cyclic Redundancy Check) field. The layer 1 frame header includes a “Packet Length” identifier, a “Priority” identifier, a “Protocol” identifier indicating the type of the data, a “Frame Mode” identifier, a “Stuff” identifier indicating whether or not stuff data is contained in the layer 1 frame, and a “Header CRC” identifier. The layer 1 frame payload contains a layer 2 frame having a layer 2 frame header and a layer 2 frame payload in which the data is packed.Type: ApplicationFiled: December 12, 2000Publication date: February 7, 2002Inventor: Motoo Nishihara
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Patent number: 6330242Abstract: A loose source routing method is provided to transfer an IP packet from a transmission source gateway to a transfer destination gateway by way of ATM nodes, which are freely designated. At the transmission source gateway, the IP packet given from a user LAN is dissolved into ATM cells containing a BOM cell whose destination address designates the transfer destination gateway. In addition, at least one pseudo BOM cell whose destination address designates an ATM node in the ATM network is added and is located at a top place of a cell stream constructed by the dissolved ATM cells. Thus, the cell stream is transferred from the transmission source gateway to the designated ATM node in accordance with the destination address of the pseudo BOM cell. The designated ATM node discards the pseudo BOM cell so that the original BOM cell is now located at the top place of the cell stream.Type: GrantFiled: July 13, 1998Date of Patent: December 11, 2001Assignee: NEC CorporationInventors: Makoto Ogawa, Motoo Nishihara, Michio Masuda, Kurenai Murakami
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Publication number: 20010049711Abstract: A pipeline processing type shaping apparatus and method in which strict shaping processing can also be implemented for a connection at various speed by adding a simplified circuit configuration. A cache portion is provided that links with the processing of a pipeline processing portion, and this cache portion manages flow information of a packet that is being processed in the pipeline processing portion. When there is a packet that belongs to the same flow, the cache portion transfers a parameter to the pipeline processing portion assuming a virtual packet in which relevant packets are all connected. The pipeline processing portion executes pipeline processing based on this virtual parameter. Consequently, also for a flow at an optional peak-rate speed (reciprocal of the input packet interval that belongs to the same flow) and in any high-speed transmission path interface, a predetermined scheduling time by shaping can always be calculated in real time.Type: ApplicationFiled: May 25, 2001Publication date: December 6, 2001Inventor: Motoo Nishihara
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Publication number: 20010046232Abstract: A storage circuit defines a first field for storing first header bits of a first payload signal of a first data unit, a second field, and a third field for storing signal first payload signal. The first header bits are equal in number to second header bits of a second payload signal of a second data unit. A division circuit divides the first header bits by a generator polynomial to produce a first error check code. The same generator polynomial is used to divide the second header bits to produce a second error check code. A remainder of division of hypothetical header bits by the generator polynomial is summed to the first error check code to produce a sum which is inserted into the second field of the storage circuit. The hypothetical header bits are greater in number than a total number of bits in the first and second fields, so that the first and second data units can be distinguished from each other by different error check results of the first and second data units.Type: ApplicationFiled: February 13, 2001Publication date: November 29, 2001Applicant: NEC CorporationInventors: Kazuo Takagi, Naoya Henmi, Shinobu Sasaki, Kurenai Murakami, Motoo Nishihara, Yoshinori Rokugou
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Patent number: 6314098Abstract: In an ATM connectionless communication system for delivering connectionless datagram in the form of sessions through an ATM network, each one of multiple edge units is connected to a user network where quality-of-service (QoS) sessions and No-QoS sessions are mixed. Each of the edge units accommodates an IPv4 packet from the user network into an intermediate frame and accommodates the intermediate frame into ATM cells. The edge units are connected to core units by permanent virtual paths to form a connectionless network. Each of the edge units has a session supervising section for determining whether the IPv4 packet is a QoS session or a No-QoS session, to allocate a control flow number to the IPv4 packet when the IP4 packet is a QoS session.Type: GrantFiled: May 12, 1998Date of Patent: November 6, 2001Assignee: NEC CorporationInventors: Michio Masuda, Motoo Nishihara, Makoto Ogawa
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Publication number: 20010007557Abstract: A datagram relaying apparatus includes a plurality of protocol terminating units, and a destination determining processor. The destination determining processor includes a path selecting section which determines a transfer destination route for a stream of packets received from any of the protocol terminating units. The path selecting section determines whether or not transfer of the received stream of packets to the transfer destination route is in an inhibition state, and selects another transfer destination route when the transfer of the packet to the transfer destination route is in the inhibition state.Type: ApplicationFiled: January 3, 2001Publication date: July 12, 2001Inventors: Kenshin Yamada, Yasuhiro Miyao, Motoo Nishihara
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Patent number: 6208653Abstract: The present invention provides a gateway unit which comprises a detecting unit for detecting the congestion from an RM cell from the ATM cell, for discriminating a TCP data gram (TCPDG) from a packet received during the congestion and for acquiring a sequence number of the TCPDG, a sending unit for sending an ACK having a window-controlled value to a transmitting terminal so as to limit a data transmission, and a discarding unit for discarding the packet from the transmitting terminal during the congestion after the confirmation of packet. During the congestion in the ATM network, a pseudo acknowledgment is sent from the gateway unit so as to indicate that the receiving terminal cannot receive data. This restrains the transmission of TCPDG from the transmitting terminal.Type: GrantFiled: March 16, 1998Date of Patent: March 27, 2001Assignee: NEC CorporationInventors: Makoto Ogawa, Motoo Nishihara, Michio Masuda
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Patent number: 6201810Abstract: In a high-speed routing control system, plural path candidates each leading to a destination node are selected on the basis of physical connection information of links connecting respective nodes in a path candidate selection unit 11, and a path candidate containing no congestion-occurring link is specified as the optimum path from the plural path candidates selected by the path candidate selection unit 11 in an optimizing unit 12. Accordingly, even when the destination node is nearer to the self node, the optimum path selection can be performed, and a switching operation to a bypass path can be performed at high speed. In addition, the traffic amount based on topology information can be suppressed, and the large-scaling of the network can be supported.Type: GrantFiled: August 13, 1997Date of Patent: March 13, 2001Assignee: NEC CorporationInventors: Michio Masuda, Motoo Nishihara, Makoto Ogawa
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Connectionless network for routing cells with connectionless address, VPI and packet-identifying VCI
Patent number: 6137798Abstract: In a connectionless communication system, a number of interworking units are provided for accommodating local area networks. At the internetworking units, a packet from the local area networks are segmented into cells for transmission to an ATM network. The cells contain a connectionless address designating a designation local area network, a virtual path identifier (VPI) designating a permanent virtual connection, and a virtual channel identifier (VCI) identifying the packet. The ATM network includes a number of cross-connect nodes interconnected by communication links. The cross-connect nodes establish a plurality of permanent virtual connections between the interworking units and the nodes and between the nodes in pairs, receive the cells from the interworking units and route the cells having VCIs of the same value through the permanent virtual connections to a destination interworking unit according to the connectionless address and the VPI contained in the cells.Type: GrantFiled: August 15, 1997Date of Patent: October 24, 2000Assignee: NEC CorporationInventors: Motoo Nishihara, Michio Masuda, Makoto Ogawa -
Patent number: 5764637Abstract: An STM/ATM converter for converting time-slot data in STM frames to ATM cells, which allows channel assignment on the STM transmission line to be flexible. In a writing operation for assembling the ATM cell, each byte data of STM frame arriving is written into a selected idle cell block which is the same size of memory capacity as an ATM cell. In a reading operation for cell output, a virtual path identifier VPI number in the FIFO 104 is read out, and in turn, the address of a cell block stored in a read address FIFO 205 corresponding to the VPI number is read out. Contends of the cell block are read out and added with overhead information for outputting as the ATM cell.Type: GrantFiled: May 9, 1996Date of Patent: June 9, 1998Assignee: NEC CorporationInventor: Motoo Nishihara
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Patent number: 5742600Abstract: The disclosed device allows de-ceiling of ATM cells in structured data transmission according to ITU-Telecommunication Recommendation I. 363, reproduction of a plurality of STM frames represented at a speed of 64 kbps.times.n (n=any natural number), and moreover, discloses an architecture that allows a minimum of the buffer amount due to the de-ceiling.Type: GrantFiled: June 5, 1996Date of Patent: April 21, 1998Assignee: NEC CorporationInventor: Motoo Nishihara