Patents by Inventor Mototsugu Okushima
Mototsugu Okushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7538995Abstract: A semiconductor IC device includes an electrostatic protective circuit connected to an internal circuit connected between two pads. The internal circuit includes a matching circuit for adjusting the impedance between the two pads. The matching circuit includes n (n is a positive number of 2 or more) resistance elements connected in parallel between the two pads; n×m (m is a positive number of 2 or more) transistors, each m transistors connected in parallel being connected in series to the n resistance elements, respectively; and an adjustor for selectively allowing the transistors to perform an ON-operation. The resistance of each resistance element is set to a larger value than the impedance to be adjusted. Accordingly, a surge-current control effect is enhanced and breakdown of the transistors can be prevented.Type: GrantFiled: December 6, 2004Date of Patent: May 26, 2009Assignee: NEC Electronics CorporationInventor: Mototsugu Okushima
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Publication number: 20090122452Abstract: A semiconductor integrated circuit includes: an output pad from which an output signal is outputted; an output signal line connected with the output pad; a first pad configured to function as a ground terminal or a power supply terminal; a first wiring connected with the first pad; an output driver connected with the output pad and configured to generate the output signal; an ESD protection device connected with the output signal line and having a function to discharge surge applied to the output pad; and a first trigger MOS transistor used as a trigger device. The output driver includes: a first protection target device connected between the output signal line and the first interconnection; and a first resistance element connected between the first protection target device and the first interconnection.Type: ApplicationFiled: November 6, 2008Publication date: May 14, 2009Applicant: NEC Electronics CorporationInventor: Mototsugu Okushima
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Publication number: 20080285190Abstract: Electrostatic protection is performed without affecting the transfer of a normal input signal. An electrostatic protection circuit includes an input terminal, aground terminal, an Nch transistor whose gate and source are coupled to the input terminal and the ground terminal, respectively, and an electrostatic protection element connected to a drain and coupled to the gate of the Nch transistor. A discharge current flows into the ground terminal through the electrostatic protection element when an electrostatic discharge is applied to the input terminal. The discharge current flows through a drain-source parasitic resistance in the Nch transistor because the Nch transistor is turned on caused by an applied voltage of the electrostatic discharge to the gate. This leads to an increase in an electric potential at Point B (channel potential) of the Nch transistor. Then, a maximum value of a voltage applied to a gate insulating film reduces lower than the voltage caused by electrostatic discharge.Type: ApplicationFiled: May 5, 2008Publication date: November 20, 2008Applicant: NEC Electronics CorporationInventor: Mototsugu Okushima
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Publication number: 20080253044Abstract: An electrostatic protection circuit that affords protection without effecting transfer of an ordinary output signal includes an output terminal; a ground terminal; a first N-channel transistor having its drain and source connected between the output terminal and the ground terminal GND; a first electrostatic protection element connecting the output terminal and the ground terminal; and a second electrostatic protection element connected the drain and gate of the first N-channel transistor. The second N-channel transistor is connected to the gate of the first N-channel transistor.Type: ApplicationFiled: April 9, 2008Publication date: October 16, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Mototsugu Okushima
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Publication number: 20080104554Abstract: An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate potentials in a plurality of current paths between pads of different two of the plurality of power supply systems, when one of an ESD current and an ESD voltage is applied between the pads. The border cell extraction unit extracts border cells from circuits of the different two of the plurality of power supply systems, wherein the circuits are included in the plurality of circuits, the border cells input and/or output signals between the circuits. The check unit checks an ESD tolerance by calculating a potential difference between the border cells, based on the calculated potentials, the extracted border cells.Type: ApplicationFiled: October 3, 2007Publication date: May 1, 2008Inventors: Susumu Kobayashi, Morihisa Hirata, Mototsugu Okushima, Tomohiro Kitayama, Tetsuya Katou
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Patent number: 7352547Abstract: A semiconductor integrated circuit device of the invention includes: a first power supply system including a first circuit connected with a first power supply line; a second power supply system including a second circuit connected with a second power supply line; a signal line connected between the first circuit and the second circuit, and transmitting a signal between the first circuit and the second circuit; a discharge path which is different from the signal line and through which an abnormal current flows when an abnormal voltage is applied between the first power supply system and the second power supply system; a detecting circuit for detecting a potential difference between two positions in the discharge path through which the abnormal current flows when the abnormal voltage is generated; and a protective circuit that operates based on an output of the detecting circuit to suppress a voltage increase of the signal line.Type: GrantFiled: May 12, 2006Date of Patent: April 1, 2008Assignee: NEC Electronics CorporationInventor: Mototsugu Okushima
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Publication number: 20080036011Abstract: Latchup is prevented from occurring accompanying increasingly finer geometries of a chip. NchMOSFET N1 and PchMOSFET P1 form a CMOS circuit including: NchMOSFET N2 whose gate, drain and back gate are connected to back gate of N1 and PchMOSFET P2 whose gate, drain and back gate are connected to back gate of P1. Source of N2 is connected to source of N1. Source of P2 is connected to source of P1. N2 is always connected between the grounded source of N1 and the back gate of N1, while P2 is connected between source of P1 connected to a power supply and the back gate of P1. Each of N2 and P2 functions as a voltage limiting element (a limiter circuit).Type: ApplicationFiled: August 6, 2007Publication date: February 14, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Mototsugu Okushima
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Patent number: 7294542Abstract: To reduce electric current concentration and electric field concentration in junction parts even in the case of miniaturization, and to achieve triggering at low voltage, an ESD protection apparatus is installed between an input terminal of a semiconductor integrated circuit chip and a CMOS transistor. The ESD protection apparatus includes a trigger element having diodes which are broken down by overvoltage applied to the input terminal and an ESD protection element including vertical bipolar transistors for discharging the accumulated electric charge of the input terminal by being electrically discharged owing to the breakdown of the diodes.Type: GrantFiled: May 30, 2006Date of Patent: November 13, 2007Assignee: NEC Electronics CorporationInventor: Mototsugu Okushima
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Publication number: 20070228476Abstract: A semiconductor device capable of dissipating heat, which has been produced in an ESD protection element, to the exterior of the device rapidly and efficiently includes an ESD protection element having a drain region, a source region and a gate electrode, and a thermal diffusion portion. The thermal diffusion portion, which has been formed on the drain region, has a metal layer electrically connected to a pad, and contacts connecting the drain region and metal layer. The metal layer has a first wiring trace extending along the gate electrode, and second wiring traces intersecting the first wiring trace perpendicularly. The contacts are connected to intersections between the first wiring trace and the second wiring traces. Heat that has been produced at a pn-junction of the ESD protection element and transferred through a contact is diffused simultaneously in three directions through the first wiring trace and second wiring trace in the metal layer and is released into the pad.Type: ApplicationFiled: March 28, 2007Publication date: October 4, 2007Applicant: NEC ELECTRONICS CORPORATIONInventor: Mototsugu Okushima
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Publication number: 20070194380Abstract: To make electric current concentration and electric field concentration hardly take place in junction parts even in case of performing miniaturization and to achieve triggering at low voltage. An ESD protection apparatus is installed between an input terminal 6 of a semiconductor integrated circuit chip and a CMOS transistor 100 and includes a trigger element 310 comprising diodes 311, 312 which are broken down by overvoltage applied to the input terminal 6 and an ESD protection element 210 including longitudinal bipolar transistors 211, 212 for discharging the accumulated electric charge of the input terminal 6 by being electrically communicated owing to the breakdown of the diodes 311, 312.Type: ApplicationFiled: January 4, 2007Publication date: August 23, 2007Inventor: Mototsugu Okushima
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Patent number: 7183612Abstract: In an ESD protecting element, a plurality of source regions and a plurality of ballast resistor regions are formed. A drain region is formed at a region which is in contact with a channel region in the ballast resistor region, and an n+ type diffusion region is formed at a region isolated from the drain region via an STI region. A third contact is provided on the drain region, first and second contacts are formed on the n+ type diffusion region, and the first contact is connected to a pad. The second contact is coupled to the third contact by a metal wire. The first and second contacts are laid out along the widthwise direction of a gate.Type: GrantFiled: December 20, 2004Date of Patent: February 27, 2007Assignee: NEC Electronics CorporationInventor: Mototsugu Okushima
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Publication number: 20060262472Abstract: A semiconductor integrated circuit device of the invention includes: a first power supply system including a first circuit connected with a first power supply line; a second power supply system including a second circuit connected with a second power supply line; a signal line connected between the first circuit and the second circuit, and transmitting a signal between the first circuit and the second circuit; a discharge path which is different from the signal line and through which an abnormal current flows when an abnormal voltage is applied between the first power supply system and the second power supply system; a detecting circuit for detecting a potential difference between two positions in the discharge path through which the abnormal current flows when the abnormal voltage is generated; and a protective circuit that operates based on an output of the detecting circuit to suppress a voltage increase of the signal line.Type: ApplicationFiled: May 12, 2006Publication date: November 23, 2006Applicant: NEC ELECTRONICS CORPORATIONInventor: Mototsugu Okushima
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Publication number: 20060223258Abstract: To reduce electric current concentration and electric field concentration in junction parts even in the case of miniaturization, and to achieve triggering at low voltage, an ESD protection apparatus is installed between an input terminal of a semiconductor integrated circuit chip and a CMOS transistor. The ESD protection apparatus includes a trigger element having diodes which are broken down by overvoltage applied to the input terminal and an ESD protection element including vertical bipolar transistors for discharging the accumulated electric charge of the input terminal by being electrically discharged owing to the breakdown of the diodes.Type: ApplicationFiled: May 30, 2006Publication date: October 5, 2006Applicant: NEC ELECTRONICS CORPORATIONInventor: Mototsugu Okushima
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Patent number: 7112852Abstract: The electrostatic protection device provided between an input/output terminal and an internal circuit of a semiconductor device according to the present invention has a first insulated gate field effect transistor (MOS transistor) and a second MOS transistor that are connected mutually in parallel between an input/output wiring connected to the input/output terminal and an electrode wiring of a prescribed potential, where the first MOS transistor and the second MOS transistor are MOS transistors of the same channel type, the second MOS transistor has s higher drive capability than the first MOS transistor, and the electrostatic protection device is formed such that it is started by the first MOS transistor.Type: GrantFiled: April 23, 2002Date of Patent: September 26, 2006Assignee: NEC Electronics CorporationInventor: Mototsugu Okushima
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Patent number: 7067884Abstract: M pieces of n-well regions nW are provided on a main surface of a p-type silicon substrate 3, and p-well regions pW are provided among the n-well regions adjacent to one another. Moreover, each of the M pieces of n-well regions nW includes an n-type diffusion region nD and a p-type diffusion region pD1, which are formed therein. Furthermore, the p-well region pW includes a p-type diffusion region pD2 therein. The n-type diffusion region nD in a j-th of the n-well region nW is connected to the p-type diffusion region pD1 in a (j+1)-th of the n-well region 10. The p-type diffusion region pD1 in the first n-well region nW is connected to a first terminal 1. The n-type diffusion region nD in the M-th of the n-well region nW is connected to a second terminal 2.Type: GrantFiled: December 22, 2003Date of Patent: June 27, 2006Assignee: NEC Electronics CorporationInventor: Mototsugu Okushima
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Publication number: 20050133839Abstract: In an ESD protecting element, a plurality of source regions and a plurality of ballast resistor regions are formed. A drain region is formed at a region which is in contact with a channel region in the ballast resistor region, and an n+ type diffusion region is formed at a region isolated from the drain region via an STI region. A third contact is provided on the drain region, first and second contacts are formed on the n+ type diffusion region, and the first contact is connected to a pad. The second contact is coupled to the third contact by a metal wire. The first and second contacts are laid out along the widthwise direction of a gate.Type: ApplicationFiled: December 20, 2004Publication date: June 23, 2005Applicant: NEC ELECTRONICS CORPORATIONInventor: Mototsugu Okushima
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Publication number: 20050122646Abstract: A semiconductor IC device includes an electrostatic protective circuit connected to an internal circuit connected between two pads. The internal circuit includes a matching circuit for adjusting the impedance between the two pads. The matching circuit includes n (n is a positive number of 2 or more) resistance elements connected in parallel between the two pads; n×m (m is a positive number of 2 or more) transistors, each m transistors connected in parallel being connected in series to the n resistance elements, respectively; and an adjustor for selectively allowing the transistors to perform an ON-operation. The resistance of each resistance element is set to a larger value than the impedance to be adjusted. Accordingly, a surge-current control effect is enhanced and breakdown of the transistors can be prevented.Type: ApplicationFiled: December 6, 2004Publication date: June 9, 2005Applicant: NEC ELECTRONICS CORPORATIONInventor: Mototsugu Okushima
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Publication number: 20040155291Abstract: M pieces of n-well regions nW are provided on a main surface of a p-type silicon substrate 3, and p-well regions pW are provided among the n-well regions adjacent to one another. Moreover, each of the M pieces of n-well regions nW includes an n-type diffusion region nD and a p-type diffusion region pD1, which are formed therein. Furthermore, the p-well region pW includes a p-type diffusion region pD2 therein. The n-type diffusion region nD in a j-th of the n-well region nW is connected to the p-type diffusion region pD1 in a (j+1)-th of the n-well region 10. The p-type diffusion region pD1 in the first n-well region nW is connected to a first terminal 1. The n-type diffusion region nD in the M-th of the n-well region nW is connected to a second terminal 2.Type: ApplicationFiled: December 22, 2003Publication date: August 12, 2004Applicant: NEC Electronics CorporationInventor: Mototsugu Okushima
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Patent number: 6512663Abstract: In an electrostatic protection device, a parasitic bipolar transistor has a base region. A trigger device is arranged adjacent to the parasitic bipolar transistor and injects charges generated by static electricity into the base region.Type: GrantFiled: May 23, 2000Date of Patent: January 28, 2003Assignee: NEC CorporationInventor: Mototsugu Okushima
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Publication number: 20020153533Abstract: The electrostatic protection device provided between an input/output terminal and an internal circuit of a semiconductor device according to the present invention has a first insulated gate field effect transistor (MOS transistor) and a second MOS transistor that are connected mutually in parallel between an input/output wiring connected to the input/output terminal and an electrode wiring of a prescribed potential, where the first MOS transistor and the second MOS transistor are MOS transistors of the same channel type, the second MOS transistor has s higher drive capability than the first MOS transistor, and the electrostatic protection device is formed such that it is started by the first MOS transistor.Type: ApplicationFiled: April 23, 2002Publication date: October 24, 2002Inventor: Mototsugu Okushima