Patents by Inventor Motoyuki Kawaba
Motoyuki Kawaba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10783983Abstract: A variant information processing device for processing genetic information includes a processor configured to create variant storage data, from variant information of each of a plurality of target individuals to be processed, where the variant information includes information of variant locus and variant pattern associated with the variant locus. The variant locus corresponds to a portion where the genetic information varies among the plurality of target individuals, the variant pattern corresponds to the genetic information of the portion, and the variant storage data includes an array region with each a first storage region with a fixed bit length and a second storage region with the fixed bit length. The code associated with the variant pattern at each of the variant locus is stored in first storage region or both of the first and second storage regions depending on the length of variant pattern associated with the code.Type: GrantFiled: February 9, 2017Date of Patent: September 22, 2020Assignee: FUJITSU LIMITEDInventors: Yoshifumi Ujibashi, Motoyuki Kawaba
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Patent number: 10528594Abstract: A database system includes a storage device which stores a database storing a plurality of data groups, range information including a minimum and a maximum of an appointed item, a total value and a number of the data, and an information processing device comprises a processor configured to, in response to deletion of a first data, update the total value and the number of the data, calculate a difference between a first total value, based on the number of the data and at least one of the maximum and the minimum in the range information, and a second total value which is updated, as minimum or maximum, judge at least one of whether or not the minimum which is calculated exceeds the minimum in the range information and whether or not the maximum which is calculated is less than the maximum in the range information, and update the range information.Type: GrantFiled: March 3, 2016Date of Patent: January 7, 2020Assignee: FUJITSU LIMITEDInventors: Yoshifumi Ujibashi, Motoyuki Kawaba
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Publication number: 20190221284Abstract: An information processing apparatus includes a memory; and a processor coupled to the memory and configured to execute processing relating to a plurality of sequences according to a plurality of variant patterns included in each of the plurality of sequences, wherein the executing the processing relating to the plurality of sequences includes: when variant patterns at a same variant position are same among the plurality of sequences, executing processing of exclusion of the same variant patterns from the plurality of sequences, and storing the plurality of sequences for which the processing of exclusion has been executed in the memory.Type: ApplicationFiled: March 26, 2019Publication date: July 18, 2019Applicant: FUJITSU LIMITEDInventors: Motoyuki Kawaba, Yoshifumi Ujibashi
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Patent number: 10324854Abstract: An information processing apparatus includes a storage device configured to have a first storage area disposed on a first memory, a second storage area disposed on a second memory being slower in speed than the first memory to be cached by using a capacity of a cache area exclusive of the first storage area on the first memory, and a third storage area disposed on the second memory without being cached, and a processor configured to increase a capacity of the third storage area while decreasing a capacity of the second storage area corresponding to the capacity of the cache area upon an increase of the capacity of the first storage area and a decrease of the capacity of the cache area.Type: GrantFiled: February 25, 2016Date of Patent: June 18, 2019Assignee: FUJITSU LIMITEDInventor: Motoyuki Kawaba
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Patent number: 9817583Abstract: An information processing device includes a processor. The processor is configured to allocate a plurality of allocation unit areas to a virtual volume from a first storage device and a second storage device. The processor is configured to generate evaluation information related to access for each of a plurality of divided areas into which each of the plurality of allocation unit areas is divided. The processor is configured to determine based on the generated evaluation information, when allocation to the virtual volume is changed from a first allocation unit area of the first storage device to a second allocation unit area of the second storage device, a first data transfer order of transferring data in divided area units from the first allocation unit area to the second allocation unit area. The processor is configured to transfer the data in accordance with the first data transfer order.Type: GrantFiled: April 23, 2014Date of Patent: November 14, 2017Assignee: FUJITSU LIMITEDInventors: Kazutaka Ogihara, Kazuichi Oe, Motoyuki Kawaba
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Patent number: 9804780Abstract: A storage apparatus is provided, including a first storage device; a second storage device having an access speed higher than an access speed of the first storage device; a monitor that monitors a write access load for the first storage device; a comparator that compares the write access load for the first storage device monitored by the monitor, with a load threshold; and a switch that causes write access target data to be written into the first and second storage devices, when it is determined by the comparator that the write access load for the first storage device does not exceed the load threshold, while causing the write access target data to be written into the first storage device, when it is determined by the comparator that the write access load for the first storage device exceeds the load threshold.Type: GrantFiled: November 4, 2014Date of Patent: October 31, 2017Assignee: FUJITSU LIMITEDInventors: Kazuichi Oe, Motoyuki Kawaba
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Publication number: 20170255453Abstract: An information processing device includes a memory and a processor coupled to the memory. The processor is configured to receive a designation of a first function within a first program. The processor is configured to: extract, from among third functions called in first function calls during execution of the first program, a second function with a call depth same as a call depth of the first function on basis of execution information. The call depth of a specific function is a number of functions traced along a sequence of second function calls from a start function to the specific function. The execution information indicates call depths of the respective third functions. The start function is a function with which the execution of the first program starts. The processor is configured to: output information of the second function.Type: ApplicationFiled: January 30, 2017Publication date: September 7, 2017Applicant: FUJITSU LIMITEDInventor: Motoyuki Kawaba
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Publication number: 20170242588Abstract: A variant information processing device for processing genetic information includes a processor configured to create variant storage data, from variant information of each of a plurality of target individuals to be processed, where the variant information includes information of variant locus and variant pattern associated with the variant locus. The variant locus corresponds to a portion where the genetic information varies among the plurality of target individuals, the variant pattern corresponds to the genetic information of the portion, and the variant storage data includes an array region with each a first storage region with a fixed bit length and a second storage region with the fixed bit length. The code associated with the variant pattern at each of the variant locus is stored in first storage region or both of the first and second storage regions depending on the length of variant pattern associated with the code.Type: ApplicationFiled: February 9, 2017Publication date: August 24, 2017Applicant: FUJITSU LIMITEDInventors: Yoshifumi Ujibashi, Motoyuki Kawaba
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Patent number: 9720600Abstract: An apparatus is connected to a first storage and a second storage which is accessed at an access speed lower than an access speed of the first storage. The apparatus accesses each of blocks stored in the second storage, and counts, for each of the blocks, the number of accesses made for the each block. The apparatus determines, based on the number of accesses that has been counted for each of the blocks, a transfer target block that is a target which is to be transferred from the second storage to the first storage, and determines a transfer time at which transfer of the transfer target block is to be performed. The apparatus transfers the determined transfer target block to the first storage at the determined transfer time.Type: GrantFiled: May 15, 2014Date of Patent: August 1, 2017Assignee: FUJITSU LIMITEDInventors: Motoyuki Kawaba, Kazuichi Oe, Kazutaka Ogihara
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Patent number: 9634825Abstract: A first memory unit stores requester event information pieces each including time information indicating an occurrence time of an event associated with a process executed by a first server. A second memory unit stores request-destination event information pieces each including time information indicating an occurrence time of an event associated with a process executed by a second server in response to a request from the first server. A determining unit determines, for each request-destination event information piece, a correction allowable range of the time information by comparing the time information of the request-destination event information pieces with that of the requester event information pieces.Type: GrantFiled: June 16, 2014Date of Patent: April 25, 2017Assignee: FUJITSU LIMITEDInventors: Toshihiro Shimizu, Motoyuki Kawaba, Yuuji Hotta
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Patent number: 9594519Abstract: From unit storage areas each having a certain size in a first storage device, an extraction unit extracts, at certain time intervals, a monitored area formed by consecutive unit storage areas having been accessed at least a predetermined number of times that is greater than zero and being similar to each other in the number of times of access. When detecting movement between the positions of same-sized monitored areas among the extracted monitored areas over time, a prediction unit determines a predicted storage area predicted to be accessed in the storage area of the first storage device on the basis of the direction of the movement between the positions of the same-sized monitored areas, and performs a control operation so that the content of the predicted storage area is copied to a second storage device that provides faster access than the first storage device.Type: GrantFiled: April 9, 2015Date of Patent: March 14, 2017Assignee: FUJITSU LIMITEDInventors: Satoshi Iwata, Kazuichi Oe, Motoyuki Kawaba
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Patent number: 9582550Abstract: A first memory stores requester event records describing events that occurred in relation to processes executed in a first server. A second memory stores requestee event records describing events that occurred in relation to processes executed in a second server in response to execution requests issued from the first server. An associating unit searches the first and second memories for requester event records and requestee event records whose transaction identifiers are identical and associates the found records together. A determining unit compares the associated event records with each other in terms of their time information. Based on this comparison, the determining unit determines a correction value for correcting time differences between requester event records in the first memory and requestee event records in the second memory.Type: GrantFiled: April 1, 2014Date of Patent: February 28, 2017Assignee: FUJITSU LIMITEDInventors: Yuuji Hotta, Motoyuki Kawaba, Toshihiro Shimizu, Yasuhiko Kanemasa
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Publication number: 20160357847Abstract: A method includes: reading, when each of a plurality of pieces of data is set as target data to be grouped and the target data is grouped based on boundary value of a root node in a binary tree, the target data from the plurality of pieces of data, specifying a temporary maximum value that indicates a maximum value among the target data and data already grouped, and a temporary minimum value that indicates a minimum value among the target data to be grouped and the data already grouped; specifying a maximum value and a minimum value of the plurality of pieces of data by updating the temporary maximum value and the temporary minimum value; and dividing the plurality of pieces of data based on a boundary value between the maximum value and the minimum value of the plurality of pieces of data among the plurality of boundary values.Type: ApplicationFiled: May 31, 2016Publication date: December 8, 2016Applicant: FUJITSU LIMITEDInventors: Tsuguchika Tabaru, Motoyuki Kawaba
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Publication number: 20160291975Abstract: A method of compiling a program that executes a plurality of unit processes in parallel, the method includes: replacing a load instruction of a volatile variable, the volatile variable being a variable included in the program and having a possibility of being overwritten by another unit process, with a beginning load instruction indicating a beginning of a range of transactionization and a load, and an end instruction indicating an ending of the range of the transactionization; moving the beginning load instruction before a position of the load instruction of the volatile variable in the program by instruction scheduling; and generating a beginning instruction indicating a beginning of a range of the transactionization and a load instruction of the volatile variable from the moved beginning load instruction.Type: ApplicationFiled: January 29, 2016Publication date: October 6, 2016Applicant: FUJITSU LIMITEDInventors: Takushi HASHIDA, Minoru Nakamura, Motoyuki Kawaba
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Publication number: 20160283393Abstract: An information processing apparatus includes a storage device configured to have a first storage area disposed on a first memory, a second storage area disposed on a second memory being slower in speed than the first memory to be cached by using a capacity of a cache area exclusive of the first storage area on the first memory, and a third storage area disposed on the second memory without being cached, and a processor configured to increase a capacity of the third storage area while decreasing a capacity of the second storage area corresponding to the capacity of the cache area upon an increase of the capacity of the first storage area and a decrease of the capacity of the cache area.Type: ApplicationFiled: February 25, 2016Publication date: September 29, 2016Applicant: FUJITSU LIMITEDInventor: Motoyuki Kawaba
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Publication number: 20160267162Abstract: A database system includes a storage device which stores a database storing a plurality of data groups, range information including a minimum and a maximum of an appointed item, a total value and a number of the data, and an information processing device comprises a processor configured to, in response to deletion of a first data, update the total value and the number of the data, calculate a difference between a first total value, based on the number of the data and at least one of the maximum and the minimum in the range information, and a second total value which is updated, as minimum or maximum, judge at least one of whether or not the minimum which is calculated exceeds the minimum in the range information and whether or not the maximum which is calculated is less than the maximum in the range information, and update the range information.Type: ApplicationFiled: March 3, 2016Publication date: September 15, 2016Applicant: FUJITSU LIMITEDInventors: Yoshifumi Ujibashi, Motoyuki Kawaba
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Patent number: 9348516Abstract: A storage system includes: a first storage unit; a second storage unit that has an access speed higher than an access speed of the first storage unit; and a storage controller that collects load information about respective loads in a plurality of areas in the first storage unit, selects a candidate area in the first storage unit which is to be migrated, based on the collected load information, and migrates data in the selected candidate area, to the second storage unit.Type: GrantFiled: November 25, 2013Date of Patent: May 24, 2016Assignee: FUJITSU LIMITEDInventors: Kazuichi Oe, Motoyuki Kawaba
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RECORDING MEDIUM STORING ACCESS CONTROL PROGRAM, ACCESS CONTROL APPARATUS, AND ACCESS CONTROL METHOD
Publication number: 20160041769Abstract: An access control apparatus includes a processor that executes a process including: reading first consecutive blocks from a storage device in response to an access request for a first data, the first consecutive blocks including a first block, storage areas of the storage device being managed in units of blocks; loading the first consecutive blocks into a memory area, storage areas of the memory area being managed in units of pages; and in accordance with a state of an access to a page in the memory area, invalidating a specific block of the storage device that corresponds to a specific page pushed out of the memory area, the specific page being pushed out as a consequence of loading the first consecutive blocks into the memory area, and writing second data included in the specific page to consecutive empty areas of the storage device.Type: ApplicationFiled: August 4, 2015Publication date: February 11, 2016Applicant: FUJITSU LIMITEDInventors: Hidekazu TAKAHASHI, Miho Murata, Kazutaka OGIHARA, Motoyuki Kawaba -
Patent number: 9251032Abstract: In an information processing apparatus, a calculation unit retrieves data that indicates processing periods of processes executed in each time window constituting an analysis period. The calculation unit then calculates a total processing time for each time window by adding up processing times spent for execution of processes. The calculation unit also calculates a total progress quantity for each time window by adding up progress quantities of the processes. A determination unit determines, based on the total processing time and total progress quantity of each time window, a threshold of the total processing times at which the ratio of an increase of the total progress quantity to an increase of the total processing time is equal to or smaller than a predetermined value. A detection unit detects time windows whose total processing times are equal to or longer than the threshold.Type: GrantFiled: November 3, 2011Date of Patent: February 2, 2016Assignees: FUJITSU LIMITED, THE GEORGIA TECH RESEARCH CORPORATIONInventors: Yasuhiko Kanemasa, Motoyuki Kawaba, Calton Pu, Qingyang Wang
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Publication number: 20160011989Abstract: An access control apparatus includes a processor. The processor is configured to receive an access request for accessing first data. The processor is configured to read consecutive blocks that start with a first block containing the first data from a first storage unit. The processor is configured to load the consecutive blocks as corresponding consecutive pages into a memory area. The processor is configured to invalidate the consecutive blocks in the first storage unit. The processor is configured to write, before the loading, some of first pages held in the memory area into a contiguous empty area of the first storage unit in accordance with an access status of each of the first pages. The access status is whether each of the first pages has been accessed.Type: ApplicationFiled: July 2, 2015Publication date: January 14, 2016Applicant: FUJITSU LIMITEDInventors: Hidekazu TAKAHASHI, Miho Murata, Kazutaka OGIHARA, Motoyuki Kawaba