Abstract: A wavelength multiplexing optical fiber transmitter, receiver, or transceiver where multiple emitters and/or photodetectors of different center wavelengths are coupled to a single optical fiber core terminus through multiple waveguides, which may be directly printed in free space. The optical assemblies described are suitable for optical data link applications, for example, to reduce a number of optical fibers needed for a given bandwidth or increase the bandwidth of a give number of optical fibers. Bidirectional fiber termination may also be implemented with an emitter and a photodetector pair coupled to a single optical fiber core terminus through multiple waveguides.

Abstract: Disclosed are multi-phase coupled resonant clock generation circuits that include magnetic coupling compensation techniques. Also disclosed are resonant distribution circuits that can use inductors spaced more closely to one another.

Abstract: Embodiments herein relate to an equalizer in a communication system. In an example implementation, the communication system is an optical system including a Vertical-Cavity Surface-Emitting Laser (VCSEL). A transfer function of the equalizer has two complex-zeroes to compensate for a group delay variation due to an underdamped complex-pole pair of the VCSEL optical response. The equalizer may include a first transistor having a control gate coupled to an input path, a drain coupled to an output path, and a source, and first, second and third paths coupled between the source and ground. The first path includes, in series, a resistor, a node and a capacitor, the second path includes a second transistor having a control gate coupled to the node, and the third path includes a capacitor. A tuning process can be used to achieve a desired frequency and quality factor.

Abstract: Methods and apparatus are disclosed for complex-zero equalizers. An example circuit comprises driver circuitry including a first input, and equalizer circuitry including a second input, a first output coupled to the first input, a transistor including a gate terminal, a drain terminal, and a source terminal, the gate terminal coupled to the second input and the drain terminal coupled to the first output, an inductor including a first inductor terminal and a second inductor terminal, the first inductor terminal coupled to the source terminal of the transistor, a resistor coupled to the second inductor terminal, and a capacitor including a first terminal and a second terminal coupled to the source terminal and to the first inductor terminal and the second terminal coupled to ground.

Abstract: Systems, apparatuses and methods include technology that executes, with a first plurality of panels, a first matrix-matrix multiplication operation of a first layer of an optical neural network (ONN) to generate output optical signals based on input optical signals that pass through an optical path of the ONN, and weights of the first layer of the ONN. The first plurality of panels includes an input panel, a weight panel and a photodetector panel. The executing includes generating, with the input panel, the input optical signals, where the input optical signals represent an input to the first matrix-matrix multiplication operation of the first layer of the ONN, representing, with the weight panel, the weights of the first layer of the ONN, and generating, with the photodetector panel, output photodetector signals based on the output optical signals that are generated based on the input optical signals and the weights.

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

Abstract: When an output of a driver circuit is coupled with a coupled-resonator network and a clock distribution network, the driver circuit generates a clock signal comprised of first and second components at first and second frequencies. The second frequency is a harmonic of the first frequency, and the first and second frequencies are in phase. In operation, the coupled-resonator network simultaneously resonates at both the first and second frequencies when coupled with the output of the driver circuit and the clock distribution network. The coupled-resonator network comprises a first inductor and a second inductor that, in operation, are both magnetically coupled and electrically coupled. The driver circuit and coupled-resonator network cooperate to provide a clock signal to the clock distribution network with improvements in slew rate and energy efficiency.

Abstract: An integrated circuit having a transmission-line-based resonant clock distribution network for distributing a clock signal to one or more nodes, the integrated circuit including a transmission-line-based resonant network formed by one or more clock distribution units. Each clock distribution unit includes a transmission line segment having first and second ends and a resonant circuit connected to the transmission line segment at a position equidistant from the first end and the second end, where the resonant circuit includes an inductor connected in parallel with a capacitor such that the resonant circuit, along with the transmission line segment, collectively has a resonant frequency about a frequency of the clock signal.

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Abstract: An apparatus is provided which comprises: a first power supply rail to provide a first power supply; second and third power supply rails to provide second and third power supplies, respectively, wherein a voltage level of the first power supply is higher than a voltage level of each of the second and third power supplies; a first driver circuitry coupled to the first power supply rail and the second power supply rail; a second driver circuitry coupled to the third power supply rail, and coupled to the first driver circuitry; and a stack of transistors of N conductivity type coupled to the first power supply rail, and to the second driver circuitry.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

Abstract: An apparatus is provided which comprises: a first power supply rail to provide a first power supply; second and third power supply rails to provide second and third power supplies, respectively, wherein a voltage level of the first power supply is higher than a voltage level of each of the second and third power supplies; a first driver circuitry coupled to the first power supply rail and the second power supply rail; a second driver circuitry coupled to the third power supply rail, and coupled to the first driver circuitry; and a stack of transistors of N conductivity type coupled to the first power supply rail, and to the second driver circuitry.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Abstract: Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.