Patents by Inventor Mozhgan Mansuri
Mozhgan Mansuri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170243627Abstract: Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.Type: ApplicationFiled: February 18, 2016Publication date: August 24, 2017Inventors: Mozhgan Mansuri, Aaron Martin, James A. McCall
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Publication number: 20160241249Abstract: Described is an apparatus which comprises: an asynchronous clock generator to generate an asynchronous clock signal; a digital sampler for sampling a signal using the asynchronous clock signal; a duty cycle corrector (DCC) to receive a differential input clock and to generate a differential output clock, wherein the digital sampler to sample at least one of an output clock from the differential output clock; and a counter to count output of the digital sampler and to provide a control to the DCC to adjust duty cycle of the differential output clock.Type: ApplicationFiled: November 19, 2013Publication date: August 18, 2016Inventors: Ganesh BALAMURUGAN, Mozhgan MANSURI, Sami HYVONEN, Bryan K. CASPER, Frank O'MAHONY
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Patent number: 9116204Abstract: An all-digital delay measurement circuit (DMC) constructed on an integrated circuit (IC) die characterizes clocking circuits such as full phase rotation interpolators, also constructed on the IC die. The on-die all-digital DMC produces a digital output value proportional to the relative delay between two clocks, normalized to the clock period of the two clocks.Type: GrantFiled: March 30, 2012Date of Patent: August 25, 2015Assignee: Intel CorporationInventors: Frank O'Mahony, Bryan K. Casper, Mozhgan Mansuri
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Publication number: 20150161005Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.Type: ApplicationFiled: February 13, 2015Publication date: June 11, 2015Inventors: Bryan K. Casper, Stephen R. Mooney, David Dunning, Mozhgan Mansuri, James E. Jaussi
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Patent number: 8984189Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.Type: GrantFiled: May 1, 2012Date of Patent: March 17, 2015Assignee: Intel CorporationInventors: Bryan Casper, Randy Mooney, Dave Dunning, Mozhgan Mansuri, James E. Jaussi
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Publication number: 20140203798Abstract: An all-digital delay measurement circuit (DMC) constructed on an integrated circuit (IC) die characterizes clocking circuits such as full phase rotation interpolators, also constructed on the IC die. The on-die all-digital DMC produces a digital output value proportional to the relative delay between two clocks, normalized to the clock period of the two clocks.Type: ApplicationFiled: March 30, 2012Publication date: July 24, 2014Inventors: Frank O'Mahony, Bryan K. Casper, Mozhgan Mansuri
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Patent number: 8612809Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.Type: GrantFiled: December 31, 2009Date of Patent: December 17, 2013Assignee: Intel CorporationInventors: Bryan Casper, Randy Mooney, Dave Dunning, Mozhgan Mansuri, James E. Jaussi
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Patent number: 8571513Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.Type: GrantFiled: July 2, 2012Date of Patent: October 29, 2013Assignee: Intel CorporationInventors: Frank O'Mahony, Bryan Casper, James Jaussi, Matthew B. Haycock, Joseph Kennedy, Mozhgan Mansuri, Stephen R. Mooney
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Publication number: 20120281323Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.Type: ApplicationFiled: July 2, 2012Publication date: November 8, 2012Inventors: Frank O'Mahony, Bryan Casper, James Jaussi, Matthew B. Haycock, Joseph Kennedy, Mozhgan Mansuri, Stephen R. Mooney
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Publication number: 20120284436Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.Type: ApplicationFiled: May 1, 2012Publication date: November 8, 2012Inventors: Bryan Casper, Randy Mooney, Dave Dunning, Mozhgan Mansuri, James E. Jaussi
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Patent number: 8213894Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.Type: GrantFiled: December 29, 2005Date of Patent: July 3, 2012Assignee: Intel CorporationInventors: Frank O'Mahony, Bryan Casper, James Jaussi, Matthew B. Haycock, Joseph Kennedy, Mozhgan Mansuri, Stephen R. Mooney
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Publication number: 20110161748Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Inventors: Bryan Casper, Randy Mooney, Dave Dunning, Mozhgan Mansuri, James E. Jaussi
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Patent number: 7961039Abstract: Some embodiments include a tunable bandpass filter to provide a filtered output signal; a circuit portion to provide an output signal in response to the filtered output signal; a comparator circuit to provide a comparison signal in response to the output signal from the circuit portion; and a feedback circuit to tune the tunable bandpass filter in response to the comparison signal provided by the comparator circuit. Other embodiments are described and claimed.Type: GrantFiled: August 5, 2009Date of Patent: June 14, 2011Assignee: Intel CorporationInventors: Bryan K. Casper, Timothy Hollis, James E. Jaussi, Stephen R. Mooney, Frank O'Mahony, Mozhgan Mansuri
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Patent number: 7710210Abstract: An apparatus is provided that includes an injection locked oscillator and a transmitting device. The injection locked oscillator to receive a first clock signal and to provide a second clock signal by skewing the first clock signal. The transmitting device to receive an input signal and to receive the second clock signal as a clocking signal, the transmitting device to transmit an output signal based on the received clocking signal.Type: GrantFiled: September 27, 2007Date of Patent: May 4, 2010Assignee: Intel CorporationInventors: Bryan K. Casper, Mozhgan Mansuri, Frank O'Mahony, James E. Jaussi
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Patent number: 7697601Abstract: In some embodiments, equalizer circuits with controllably variable offsets at their outputs are provided.Type: GrantFiled: November 7, 2005Date of Patent: April 13, 2010Assignee: Intel CorporationInventors: Mozhgan Mansuri, Frank O'Mahony, Bryan K. Casper, James E. Jaussi
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Patent number: 7683729Abstract: In general, in one aspect, the disclosure describes an apparatus that includes an inductive capacitive voltage controlled oscillator (LC VCO) to generate an output clock. A voltage to current converter is used to receive a forwarded clock and to inject the forwarded clock to the LC VCO. The output clock is a deskewed version of the forwarded clock.Type: GrantFiled: March 30, 2007Date of Patent: March 23, 2010Assignee: Intel CorporationInventors: Mozhgan Mansuri, Sudip Shekhar, Bryan K. Casper, Frank P. O'Mahony
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Publication number: 20090289700Abstract: Some embodiments include a tunable bandpass filter to provide a filtered output signal; a circuit portion to provide an output signal in response to the filtered output signal; a comparator circuit to provide a comparison signal in response to the output signal from the circuit portion; and a feedback circuit to tune the tunable bandpass filter in response to the comparison signal provided by the comparator circuit. Other embodiments are described and claimed.Type: ApplicationFiled: August 5, 2009Publication date: November 26, 2009Inventors: Bryan K. Casper, Timothy Hollis, James E. Jaussi, Stephen R. Mooney, Frank O'Mahony, Mozhgan Mansuri
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Patent number: 7573326Abstract: A tunable bandpass filter to provide a filtered differential clock signal in response to an input differential clock signal, where an embodiment comprises a transistor pair loaded by tunable loads, and a feedback circuit to tune the tunable loads. In some embodiments, the feedback circuit tunes the loads to maximize a small-signal differential gain. In other embodiments, the feedback circuit tunes the loads to minimize a metric indicative of jitter in the filtered differential clock signal. Other embodiments are described and claimed.Type: GrantFiled: December 30, 2005Date of Patent: August 11, 2009Assignee: Intel CorporationInventors: Bryan K. Casper, Timothy Hollis, James E. Jaussi, Stephen R. Mooney, Frank O'Mahony, Mozhgan Mansuri
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Publication number: 20090086871Abstract: An apparatus is provided that includes an injection locked oscillator and a transmitting device. The injection locked oscillator to receive a first clock signal and to provide a second clock signal by skewing the first clock signal. The transmitting device to receive an input signal and to receive the second clock signal as a clocking signal, the transmitting device to transmit an output signal based on the received clocking signal.Type: ApplicationFiled: September 27, 2007Publication date: April 2, 2009Inventors: Bryan K. Casper, Mozhgan Mansuri, Frank O'Mahony, James E. Jaussi
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Publication number: 20080238503Abstract: In general, in one aspect, the disclosure describes an apparatus that includes an inductive capacitive voltage controlled oscillator (LC VCO) to generate an output clock. A voltage to current converter is used to receive a forwarded clock and to inject the forwarded clock to the LC VCO. The output clock is a deskewed version of the forwarded clock.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Inventors: Mozhgan Mansuri, Sudip Shekhar, Bryan K. Casper, Frank P. O'Mahony