Abstract: A device includes a semiconductor fin, a gate dielectric on sidewalls of the semiconductor fin, a gate electrode over the gate dielectric, and isolation regions. The isolation regions include a first portion on a side of the semiconductor fin, wherein the first portion is underlying and aligned to a portion of the gate electrode. The semiconductor fin is over a first top surface of the first portion of the isolation regions. The isolation regions further include second portions on opposite sides of the portion of the gate electrode. The second top surfaces of the second portions of the isolation regions are higher than the first top surface of the isolation regions.

Abstract: A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 ?, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region.

Abstract: A transistor including a gate structure with a first portion and a second portion; the first and second portions each have a first edge and an opposing second edge that are substantially collinear. The gate structure also includes an offset portion interposing the first portion and the second portion. The offset portion has a third edge and an opposing fourth edge. The third edge and the fourth edge are non-collinear with the first and second edges of the first and second portions of the gate structure. For example, the offset portion is offset or shifted from the first and second portions.

Abstract: A method of fabricating a semiconductor device includes forming a plurality of line element on a provided substrate. The plurality of line elements includes a first line element having a first region having a first width and a biased region having a second width. The second width different than the first width. Spacer elements are then formed abutting sidewalls of each of the plurality of line elements including the biased region where the spacer elements may be shifted. After forming the spacer elements, the plurality of line elements from the substrate are removed from the substrate. An underlying layer is etched using the spacer elements after removing the plurality of line elements.

Abstract: A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region.

Abstract: A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 ?, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including a first device disposed in a first device region, the first device including a first gate structure, first gate spacers formed on the sidewalls of the first gate structure, and first source and drain features and a second device disposed in a second device region, the second device including a second gate structure, second gate spacers formed on the sidewalls of the second gate structure, and second source and drain features. The semiconductor device further includes a contact etch stop layer (CESL) disposed on the first and second gate spacers and interconnect structures disposed on the first and second source and drain features. The interconnect structures are in electrical contact with the first and second source and drain features and in contact with the CESL.

Abstract: System and method for forming lightly doped drain (LDD) extensions. An embodiment comprises forming a gate electrode on a semiconductor fin and forming a dielectric layer over the gate electrode. The gate electrode is then etched to expose a portion of the semiconductor fin. The exposed portions of the fin comprise the LDD extensions.

Abstract: A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region.

Abstract: A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 ?, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region.

Abstract: A semiconductor structure can include a resistor on a substrate formed simultaneously with other devices, such as transistors. A diffusion barrier layer formed on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor at the same manner and time as the gate of the transistor. The filler material is removed to form a resistor on a substrate.

Abstract: System and method for forming lightly doped drain (LDD) extensions. An embodiment comprises forming a gate electrode on a semiconductor fin and forming a dielectric layer over the gate electrode. The gate electrode is then etched to expose a portion of the semiconductor fin. The exposed portions of the fin comprise the LDD extensions.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including a first device disposed in a first device region, the first device including a first gate structure, first gate spacers formed on the sidewalls of the first gate structure, and first source and drain features and a second device disposed in a second device region, the second device including a second gate structure, second gate spacers formed on the sidewalls of the second gate structure, and second source and drain features. The semiconductor device further includes a contact etch stop layer (CESL) disposed on the first and second gate spacers and interconnect structures disposed on the first and second source and drain features. The interconnect structures are in electrical contact with the first and second source and drain features and in contact with the CESL.

Abstract: A device includes a semiconductor fin, a gate dielectric on sidewalls of the semiconductor fin, a gate electrode over the gate dielectric, and isolation regions. The isolation regions include a first portion on a side of the semiconductor fin, wherein the first portion is underlying and aligned to a portion of the gate electrode. The semiconductor fin is over a first top surface of the first portion of the isolation regions. The isolation regions further include second portions on opposite sides of the portion of the gate electrode. The second top surfaces of the second portions of the isolation regions are higher than the first top surface of the isolation regions.

Abstract: A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region.

Abstract: A method of fabricating a semiconductor device includes forming a plurality of line element on a provided substrate. The plurality of line elements includes a first line element having a first region having a first width and a biased region having a second width. The second width different than the first width. Spacer elements are then formed abutting sidewalls of each of the plurality of line elements including the biased region where the spacer elements may be shifted. After forming the spacer elements, the plurality of line elements from the substrate are removed from the substrate. An underlying layer is etched using the spacer elements after removing the plurality of line elements.

Abstract: A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer.

Abstract: A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer.

Abstract: A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer.

Abstract: A semiconductor structure includes a semiconductor substrate; a first gate dielectric on the semiconductor substrate; a first gate electrode over the first gate dielectric; a first lightly doped source or drain (LDD) region in the semiconductor substrate and adjacent the first gate dielectric, wherein the first LDD region comprises arsenic; and a first deep source/drain region in the semiconductor substrate and adjacent the first gate dielectric. The first deep source/drain region comprises phosphorous, and a first phosphorous junction depth in the first deep source/drain region is greater than about three times a first arsenic junction depth in the first deep source/drain region.