Abstract: The types of quasi-planar CMOS and FinFET-like transistor devices on a bulk silicon substrate are disclosed. A first device has a doped and recessed channel formed in a shallow trench sidewall. A second device has a doped, recessed channel and has a plurality of edge-fins juxtaposed on an edge of an active region of the device. A third device has an undoped recessed channel formed in a sidewall of a shallow trench, wherein the undoped recessed channel further has a plurality of edge-fins disposed thereon. Additionally, an extra mask may be added to each device to allow for fabrication of both conventional transistors and FinFET-like transistors on bulk silicon. The extra mask may protect the source and drain areas from recess etching of the silicon substrate. Several methods of fabricating each device are also disclosed.

Abstract: A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer.

Abstract: A semiconductor structure includes a semiconductor substrate; a first gate dielectric on the semiconductor substrate; a first gate electrode over the first gate dielectric; a first lightly doped source or drain (LDD) region in the semiconductor substrate and adjacent the first gate dielectric, wherein the first LDD region comprises arsenic; and a first deep source/drain region in the semiconductor substrate and adjacent the first gate dielectric. The first deep source/drain region comprises phosphorous, and a first phosphorous junction depth in the first deep source/drain region is greater than about three times a first arsenic junction depth in the first deep source/drain region.

Abstract: A semiconductor device including a contact etch stop layer and contact hole formation method for reduced underlying material loss and improved device performance, the method including providing a semiconductor substrate including an active region including a CMOS device, STI structures, and metal silicide regions; forming a fluorine doped amorphous carbon layer over the active region; forming a PMD layer on the fluorine doped amorphous carbon layer; dry etching contact holes in the PMD layer to expose the fluorine doped amorphous carbon layer; and, removing the fluorine doped amorphous carbon layer according to a dry stripping process.

Abstract: A semiconductor device including a contact etch stop layer and contact hole formation method for reduced underlying material loss and improved device performance, the method including providing a semiconductor substrate including an active region including a CMOS device, STI structures, and metal silicide regions; forming a fluorine doped amorphous carbon layer over the active region; forming a PMD layer on the fluorine doped amorphous carbon layer; dry etching contact holes in the PMD layer to expose the fluorine doped amorphous carbon layer; and, removing the fluorine doped amorphous carbon layer according to a dry stripping process.

Abstract: The types of quasi-planar CMOS and FinFET-like transistor devices on a bulk silicon substrate are disclosed. A first device has a doped and recessed channel formed in a shallow trench sidewall. A second device has a doped, recessed channel and has a plurality of edge-fins juxtaposed on an edge of an active region of the device. A third device has an undoped recessed channel formed in a sidewall of a shallow trench, wherein the undoped recessed channel further has a plurality of edge-fins disposed thereon. Additionally, an extra mask may be added to each device to allow for fabrication of both conventional transistors and FinFET-like transistors on bulk silicon. The extra mask may protect the source and drain areas from recess etching of the silicon substrate. Several methods of fabricating each device are also disclosed.

Abstract: A new method is provided for the creation of an aluminum contact pad. A layer of passivation is created over the surface of a substrate, an opening is created through the layer of passivation. A layer of aluminum is deposited over the surface of the deposited layer of passivation, filling the opening that has been created there-through. The deposited layer of aluminum is then polished down to the surface of the layer of passivation, leaving the deposited aluminum in place inside the opening created through the layer of passivation for purposes of serving as a contact pad.

Abstract: A method of forming a pocket implant region, to reduce short channel effects (SCE), for narrow channel length, NMOS devices, has been developed. After forming an indium pocket implant region, in the area of a P type semiconductor to be used to accommodate an N type source/drain region, an ion implantation procedure is used to place antimony ions in the indium pocket implant region. The presence of antimony ions limits the broadening of the indium pocket implant profile during subsequent anneal procedures, used to activate implanted ions. Formation of an implanted, lightly doped, N type source/drain region, insulator spacers on the sides of a gate structure, and formation of a heavily doped, N type, source/drain region, complete the process sequence used to form the NMOS, transfer gate transistor.

Abstract: A method of forming an implanted pocket region, to reduce short channel effects (SCE), for narrow channel length, NMOS devices, has been developed. After forming an initial indium pocket region, with an initial indium profile, in the area of a P type semiconductor to be used to accommodate an N type source/drain region, a low temperature anneal procedure is used to activate indium ions in the initial indium pocket region, and to create a final indium pocket region, featuring a final indium profile. The final indium profile remains unchanged after experiencing subsequent high temperature procedures, such as a post-heavily doped, source/drain anneal. The narrow channel length NMOS devices, fabricated using the low temperature anneal procedure described in this invention, resulted in a reduced Vt roll-off phenomena, when compared to counterpart, narrow channel length NMOS, formed without the benefit of the low temperature anneal procedure.

Abstract: A process for fabricating input/output, N channel, (I/O NMOS) devices, featuring an ion implanted nitrogen region, used to reduce hot carrier electron, (HEC), injection, has been developed. The process features implanting a nitorgen region, at the interface of an overlying silicon oxide layer, and an underlying lightly doped source/drain, (LDD), region. The implantation procedure can either be performed prior to, or after, the deposition of a silicon oxide liner layer, in both cases resulting in a desired nitrogen pile-up at the oxide-LDD interface, as well as resulting, in a more graded LDD profile. An increase in the time to fail, in regards to HCE injection, for these I/O NMOS devices, is realized, when compared to counterparts fabricated without the nitrogen implantation procedure.

Abstract: A process for fabricating input/output, N channel, (I/O NMOS) devices, featuring an ion implanted nitrogen region, used to reduce hot carrier electron, (HEC), injection, has been developed. The process features implanting a nitorgen region, at the interface of an overlying silicon oxide layer, and an underlying lightly doped source/drain, (LDD), region. The implantation procedure can either be performed prior to, or after, the deposition of a silicon oxide liner layer, in both cases resulting in a desired nitrogen pile-up at the oxide-LDD interface, as well as resulting, in a more graded LDD profile. An increase in the time to fail, in regards to HCE injection, for these I/O NMOS devices, is realized, when compared to counterparts fabricated without the nitrogen implantation procedure.