Abstract: An electrostatic discharge protection device, including a silicon-control-rectifier, in complementary metal-oxide semiconductor (CMOS) process is disclosed. in one embodiment of the present invention, the protection device includes a semiconductor substrate having a first conductivity type. A well region formed with a second conductivity type in the semiconductor substrate. A first region formed in the well region. A second region formed having a portion in the weil region and another portion outside the well region, but still within the semiconductor substrate. Moreover, a third region formed within the well region and in between the first; region and the second region. A fourth region formed within the semiconductor substrate and outside the well region. A fifth region formed within the semiconductor substrate and in between the second region and the fourth region.

Abstract: An electrostatic discharge protection device, including a silicon-control-rectifier, in complementary metal-oxide semiconductor (CMOS) process is disclosed. In one embodiment of the present invention, the protection device includes a semiconductor substrate having a first conductivity type. A well region formed with a second conductivity type in the semiconductor substrate. A first region formed within the semiconductor substrate and outside the well region. A second region formed within the semiconductor substrate and in between the first region and the well region. Moreover, a third region formed having a portion in the well region and another portion outside the well region. A fourth region formed in the well region. A fifth region also formed within the well region and in between the third region and the fourth region.

Abstract: A device structure and a method of fabricating an electrostatic discharge (ESD) protection circuit on a semiconductor device. A substrate is provided. A layer of silicon oxide is formed on the substrate. A photoresist mask is formed on the layer of silicon oxide. A species of n-type ions is implanted into the surface to form source/drain regions in the ESD protection area. After removing the photoresist, a metal layer is blanket deposited over the surface. A thermal process is performed to form salicide layers on the source/drain regions. A patterned photoresist is respectively formed to cover a portion of the salicide layer. An etching process is performed to strip away the exposed portion of the salicide layer.

Abstract: A semiconductor device having an electrostatic discharge protective circuitry adapted to a common discharge line (CDL) is disclosed. In the embodiments of the present invention, semiconductor device includes a plurality of bonding pads, each having at least one connecting terminal, a common discharge line, and a protective device connected between the connecting terminal and the common discharge line. Moreover, the protective device is composed of a silicon-control-rectifier that is used for electrostatic discharge protection and a zener diode for lowering a trigger voltage of the silicon-control-rectifier.

Abstract: An electrostatic discharge protection device, including a silicon-control-rectifier, in complementary metal-oxide semiconductor (CMOS) process is disclosed. In one embodiment of the present invention, the protection device includes a semiconductor substrate having a first conductivity type. A well region formed with a second conductivity type in the semiconductor substrate. A first region formed within the semiconductor substrate and outside the well region. A second region formed within the semiconductor substrate and in between the first region and the well region. Moreover, a third region formed having a portion in the well region and another portion outside the well region. A fourth region formed in the well region. A fifth region also formed within the well region and in between the third region and the fourth region.

Abstract: A dielectric test structure formed over a dielectric layer. The test structure includes a first structure and a second structure. The first structure comprises a first liner pad, a second liner pad and a first conductive layer for connecting the first and the second liner pad. The second structure comprises a first section and a second section positioned symmetrically on each side of the first conductive layer but detached from the first conductive layer. The first section includes a second conductive layer parallel to the first conductive layer, a third liner pad and a third conductive layer for connecting the second conductive layer and the third liner pad. The second section includes a fourth conductive layer parallel to the first conductive layer, a fourth liner pad and a fifth conductive layer for connecting the fourth conductive layer and the fourth liner pad.

Abstract: A gate dielectric breakdown test method is disclosed. The method includes performing a one step programmed VRDB test using Vcc voltage power source, gate current density for the corresponding ramped voltages are recorded. If the gate current density is found to be higher than a specified gate current density criterion, then the gate oxide is deemed to defective and is scrapped. And, if the gate current density (Jg) is found to be less than the specified gate current density criterion (Jc), then a differential gate current density ratio R=&Dgr;Jg/Jg for the corresponding ramped voltages are calculated. If the R value is found to be less than a specified differential current density ratio criterion (Rc), then the gate dielectric is considered to be robust, and if the R value is greater than the Rc value, then the gate dielectric is considered to be inflected. Accordingly, the voltage Vg can be effectively used for justifying the integrity of the gate dielectric.

Abstract: A via plug layout structure for connecting different metallic layers. The structure includes a plurality of via plugs arranged in a fan-shaped pattern and a plurality of empty bars positioned between a single via plug and the fanned-out via plugs so that incoming current to the single via plug is equally distributed to every one of the fanned-out via plug and current stress in each fanned-out via plug is identical. Hence, via plugs having particularly serious electromigration problem can be discovered. In addition, single via plug having different critical dimension can be fabricated so that maximum critical dimension sustainable by the via plug is determined after an electromigration test.

Abstract: The present invention gives a semiconductor chip device having an integrated circuit region fabricated on a substrate, a street region surrounding the integrated circuit region, a first guard ring formed between the integrated circuit region and the street region, and a second guard ring formed between the first guard ring and the street region. The first guard ring and the second guard ring are a collection of discontinuous dam-shaped stacks to prevent die cracking when sawing the wafer.

Abstract: A gate dielectric breakdown test method is disclosed. The method includes performing a one step programmed VRDB test using Vcc voltage power source, gate current for the corresponding ramped voltages are recorded. If the gate current density is found to be higher than a specified gate current criterion, then the gate oxide is deemed to defective and is scrapped. And, if the gate current density (Jg) is found to be less than the specified gate current criterion (Jc), then a differential gate current density ratio R=Jg/Jg for the corresponding ramped voltages are calculated. If the R value is found to be less than a specified differential current density ratio criterion (Rc), then the gate dielectric is considered to be robust, and if the R value is greater than the Rc value, then the gate dielectric is considered to be inflected. Accordingly, the voltage Vg can be effectively used for justifying the integrity of the gate dielectric.

Abstract: A structure of a cross guard ring along the edge of a semiconductor chip is disclosed. A first guard ring, a second guard ring and a third guard ring are formed along the edge of a semiconductor chip. Each guard ring comprises several rectangle shaped vias which are positioned along the edge of the chip structure, wherein each rectangle via is separated from an adjacent rectangle via by a gap. Further, each rectangle via of the second guard ring is positioned opposite the said gap of the first guard ring and are crossed over and have some overlay with rectangle vias of the first guard ring which are separated by the said gap as shown in FIG. 2. Similarly the third guard ring is positioned with respect to the second guard ring.

Abstract: A structure of a cross guard ring along the edge of a semiconductor chip is disclosed. A first guard ring, a second guard ring and a third guard ring are formed along the edge of a semiconductor chip. Each guard ring comprises several rectangle shaped vias which are positioned along the edge of the chip structure, wherein each rectangle via is separated from an adjacent rectangle via by a gap. Further, each rectangle via of the second guard ring is positioned opposite the said gap of the first guard ring and are crossed over and have some overlay with rectangle vias of the first guard ring which are separated by the said gap as shown in FIG. 2. Similarly the third guard ring is positioned with respect to the second guard ring.

Abstract: A semiconductor device for preventing process-induced charging damages is disclosed. The semiconductor device comprises a semiconductor layer, at least one transistor comprising a source region, a drain region, a channel region, a gate oxide layer and a gate electrode, at least one parasitic capacitor comprising a conductive layer, a dummy conductive layer constituting a dummy pattern, and a dielectric layer interposed between the conductive layer and the dummy conductive layer, a first conductor connecting the gate electrode and the conductive layer, and a second conductor connecting the semiconductor layer and the dummy conductive layer. Furthermore, the dummy conductive layer can be a floating layer over the semiconductor layer. In such manner, the second conductor set forth is replaced by an interposed dielectric layer.

Abstract: A semiconductor structure for measuring a dielectric constant and clarifying a polarization effect of an interlevel dielectric layer is disclosed. The semiconductor structure comprises a substrate having a conductive layer thereon, an interlevel dielectric layer formed over the substrate, and a plurality of via walls formed into the interlevel dielectric layer connecting, overlapping and aligning with the conductive layer. The conductive layer comprises two areas of equidistant conductive lines and two conductive lines. Each area comprises two pluralities of equidistant conductive lines and one interposed individually between the other. The pluralities of equidistant conductive lines of the two areas are perpendicular to each other and connected by the two conductive lines. The via walls comprises pluralities of equidistant via walls connecting and aligning with the pluralities of equidistant conductive lines of the two areas.

Abstract: A semiconductor device for preventing process-induced charging damages is disclosed. The semiconductor device comprises a semiconductor layer, at least one transistor comprising a source region, a drain region, a channel region, a gate oxide layer and a gate electrode, at least one parasitic capacitor comprising a conductive layer, a dummy conductive layer constituting a dummy pattern, and a dielectric layer interposed between the conductive layer and the dummy conductive layer, a first conductor connecting the gate electrode and the conductive layer, and a second conductor connecting the semiconductor layer and the dummy conductive layer. Furthermore, the dummy conductive layer can be a floating layer over the semiconductor layer. In such manner, the second conductor set forth is replaced by an interposed dielectric layer.

Abstract: A method of manufacturing a passivation layer. A substrate having semiconductor devices thereon is provided. A dielectric layer is next formed over the substrate. A liner layer is formed over the dielectric layer. A bonding pad for electrically connecting the semiconductor device in the substrate with an external package frame is formed over the liner layer. A passivation layer is formed over the substrate to protect the circuits and devices thereon. A portion of the passivation layer is removed to expose a portion of the bonding pad. Wire-bonding operation is finally carried out to put wires on the bonding pad.

Abstract: A semiconductor device having an electrostatic discharge protective circuitry adapted to a common discharge line (CDL) is disclosed. In the embodiments of the present invention, semiconductor device includes a plurality of bonding pads, each having at least one connecting terminal, a common discharge line, and a protective device connected between the connecting terminal and the common discharge line. Moreover, the protective device composes of a silicon-control-rectifier that is used for electrostatic discharge protection and a zener diode for lowering a trigger voltage of the silicon-control-rectifier.

Abstract: A method for manufacturing semiconductor device includes the steps of providing a substrate that has a gate electrode thereon, and then forming a dielectric layer over the substrate. The dielectric layer is conformal to the profile of the substrate and has a definite thickness. Thereafter, using the gate electrode and that portion of the dielectric layer next to the sidewalls of the gate electrode as a mask, a first ion implantation is carried out. Hence, a doped drain region is formed in the substrate and a channel region is formed in the substrate just under the gate electrode. Subsequently, spacers are formed over the exposed dielectric layer next to the sidewalls of the gate electrode. Finally, using a portion of the dielectric layer next to the sidewalls of the gate electrode and the spacers as a mask, a second ion implantation is carried out. Hence, source/drain regions are formed in the substrate on each side of the gate electrode.

Abstract: A method for protecting the gate oxide layer of a MOS device. The method can also be used to monitor the intensity of radiation and charged particles falling on the gate oxide layer. The method includes the provision of a substrate having a gate structure thereon and an inter-layer dielectric layer over the gate structure, wherein the gate structure further includes a gate oxide layer and a gate electrode. Thereafter, a shielding layer is formed over the inter-layer dielectric layer, and then a protection diode is formed to link the shielding to the substrate.

Abstract: A method of fabricating a protection device. A contact resistor, or a protection diode and a contact resistor are formed in a substrate. The protection diode and the contact resistor are electrically connected to a gate of a MOS so as to protect the MOS from being damaged by plasma. A multi-level interconnect is formed on the substrate, while a top metal layer of the multi-level interconnect is patterned, the electrical connection between the gate and the protection device is broken.