Abstract: A statistical method of monitoring the yield of a gate oxide layer. A voltage is applied to first test keys and second test keys to build curves showing relationship between failure distribution and charge density, wherein each of the first test keys has a first oxide area and each of the second test keys has a second oxide area. A yield of the first test keys and a yield of the second test keys up to a charge density can be obtained. The yields of the first test keys and the second test keys have a relationship as an equation of area. To obtain a yield of small test keys, a yield and area of large test keys are imported into an equation. According to operating the equation, the yield of a small gate oxide is obtained.

Abstract: A method of protecting gate oxide. A chip having a gate thereon is provided. The gate structure comprises a gate oxide layer and a gate electrode. The gate is covered by a dielectric layer. A protection layer is formed on the dielectric layer. The protection layer is pattern to remain a part of the protection layer aligned over the gate.

Abstract: A method for testing the reliability of a dielectric thin film. An exponential current ramp test is performed with a delay time to test the dielectric thin film. An exponential current ramp charge-to-breakdown distribution, which is represented by cumulative distribution failure percentage, is obtained. An exponential current ramp charge-to-breakdown at a cumulative distribution failure percentage is calculated. An exponential current ramp constant and a constant current stress constant at the cumulative distribution failure percentage are calculated. A constant current stress charge-to-breakdown at the cumulative distribution failure percentage is calculated by using a specified current density and the constant current stress constant at the cumulative distribution failure percentage. The constant current stress charge-to-breakdown at the cumulative distribution failure percentage is compared to a specified constant current stress charge-to-breakdown to determine the reliability of the dielectric thin film.

Abstract: A method of protecting a well at a floating stage. In a first conductive type substrate, a second conductive type well is formed. A first conductive type heavily doped region and a second conductive type heavily doped region are respectively formed in the first conductive type substrate and the second conductive type well. These two heavily doped regions are electrically connected with each at an early stage of fabrication process to provide a protection from being damaged during subsequent plasma process or other processes. While forming a top metal layer of a multi-level interconnect, these two heavily doped regions are disconnected, that is, open to each other, to obtain a better electrical characteristic of the device or the integrated circuit formed on the substrate.

Abstract: A low triggering voltage PD-SOI (Partially-Depleted Silicon-on-Insulator) electrostatic discharge (ESD) protection structure is disclosed.

Abstract: A method for reducing plasma charging damages is disclosed. The method includes the following steps: define cell regions and scribe line regions on a substrate. Then, form a trench region on one of the scribe line regions wherein the bottom part of the trench region is in contact with the substrate. Thereupon fill the trench region with polysilicon substances. After the filling, deposit a pad polysilicon layer on the trench region. Following the pad layer formation, construct an integrated circuit as routine practice. During the circuit fabrication, several channel regions are formed in connection with the pad layer. Next, fabricate various conductive structures on the scribe line regions and link them also to the channel regions. Any excess charge in the scribe line region would be collected by the conductive structures and directed by the channel region to the trench region for grounding.

Abstract: A circuit for evaluating the asymmetric antenna effect of a transistor pair is provided, which can be implemented by using bipolar or complementary metal oxide semiconductor (CMOS) transistors to implement a differential amplifier, with which a pair of transistors Q1 and Q2 having similar characteristics are connected. The transistors Q1 and Q2 have a structure of, for example, one polysilicon layer and three metal layers, in which a second metal layer M2 and a third metal layer M3 are used for signal input, and metal layer M1 close to the gate oxide layer of both the transistors Q1 and Q2 are used to obtain a differential antenna ratio. The differential amplifier comprises transistors Q3 and Q4 serving as an active load, and transistor Q5, which is used for adjusting the voltage gain.

Abstract: A wafer acceptance testing (WAT) method with a test key is provided. The test key structure includes a testing structure on a substrate. An inter-layer-dielectric layer covers over the substrate to isolate the testing structure. A grounded metal layer is located on the inter-layer dielectric layer. An interconnecting structure is located on the grounded metal layer. A conductive pad layer and a passivation layer are sequentially located on the interconnecting structure. The testing structure is electrically coupled to the interconnecting structure. The interconnecting structure is also electrically coupled to the conductive pad layer. The grounded metal layer is grounded without any further coupling such that the grounded metal layer is not coupled to the testing structure and the interconnecting structure.

Abstract: The present invention provides a method for preventing gate oxides on a semiconductor wafer from being damaged by electromagnetic waves or particles generated in a plasma-related process. The semiconductor wafer comprises a substrate, a plurality of gate oxides positioned separately on the substrate, a first dielectric layer positioned on the gate oxides for isolating the gate oxides, and a conducting layer positioned on the first dielectric layer having at least one testing slit with a predetermined test pattern installed above each of the gate oxides. The method first performs a predetermined plasma-related process on the surface of the semiconductor wafer. Next, an electrical test is performed to find damaged gate oxides out of the gate oxides on the substrate. Based on damages of the damaged gate oxides, the predetermined plasma-related process is adjusted to prevent gate oxides on other semiconductor wafers from being damaged in the predetermined plasma-related process.

Abstract: A method for avoiding plasma damage. In a semiconductor substrate of a first conductive type, a second conductive type well is formed. While forming the second conductive well, a high-energy dopant is doped into the semiconductor substrate. The high energy makes a depletion region between the substrate and the well have defects. A leakage path is thus formed. The leakage path can direct any charged carriers coming from plasma to avoid accumulation of the charged carriers in the well. Thus, the electrical characteristics of the well or even the quality of gate oxide formed thereon is prevented from being degraded.

Abstract: A method for preventing damage to a gate oxide layer from a floating well in a CMOS device includes a first via plug and a second via plug formed in a dielectric layer. The first via plug is coupled to a substrate and the second via plug is coupled to the well. These two via plugs are further coupled by a conductive bridge so that both the well and the substrate have the same voltage.

Abstract: A method of testing for a kink effect typically occurring during the fabrication of shallow trench isolation of a transistor in an integrated circuit. A curve of source/drain current versus gate voltage is plotted. A second order differential of the curve is performed and plotted, and the existence of a kink effect is determined by the number of the local maxima and local minima. The degree of kink effect as low as and below a 0.25 .mu.m level is determined according to the level of a global minimum value.

Abstract: An antenna effect monitor includes a transistor formed on a semiconductor substrate. The transistor gate is coupled to a doped polysilicon interconnect layer which is also coupled to an antenna effect monitoring unit. Several metal bonding pads float in an orderly fashion above the doped polysilicon interconnect layer without coupling with each other. Several small metal layers are formed in an orderly fashion above the doped polysilicon interconnect layer but are electrically coupled together by several via plugs in between. The top small metal layer is coupled to the top bonding pad. The bottom small metal layer is electrically coupled to the doped polysilicon interconnect layer. Then a passivation layer covers the substrate but leaves a pad opening to expose the top bonding pad.