Patents by Inventor Muhammad Masuduzzaman

Muhammad Masuduzzaman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210134369
    Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the fist memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 6, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Zhiping Zhang, Muhammad Masuduzzaman, Huai-Yuan Tseng, Dengtao Zhao, Deepanshu Dutta
  • Publication number: 20210134370
    Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the first memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.
    Type: Application
    Filed: December 3, 2019
    Publication date: May 6, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Zhiping Zhang, Muhammad Masuduzzaman, Huai-Yuan Tseng, Dengtao Zhao, Deepanshu Dutta
  • Publication number: 20210134372
    Abstract: A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 6, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Zhiping Zhang, Muhammad Masuduzzaman, Huai-Yuan Tseng, Peng Zhang, Dengtao Zhao, Deepanshu Dutta
  • Patent number: 10984876
    Abstract: Various methods include receiving, by a controller, a temperature reading of a memory array, the temperature reading includes a temperature value; determining the temperature value is below a first threshold; in response, modifying a duration of a verify cycle of a write operation to create a modified verify cycle; then programming a first data into the memory array using the write operation that uses the modified verify cycle. Methods additionally include receiving a second temperature reading of the memory array, the second temperature reading includes a second temperature value; determining the second temperature value is below a second threshold, in response, decreasing the duration of a verify cycle of a verify cycle to create a second verify cycle, where the second verify cycle is shorter than the modified verify cycle; and then programming a second data into the memory array using the write operation that uses the second verify cycle.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: April 20, 2021
    Assignee: SanDiskTechnologies LLC
    Inventors: Piyush Dak, Mohan Dunga, Chao Qin, Muhammad Masuduzzaman, Xiang Yang
  • Publication number: 20200402594
    Abstract: Various methods include receiving, by a controller, a temperature reading of a memory array, the temperature reading includes a temperature value; determining the temperature value is below a first threshold; in response, modifying a duration of a verify cycle of a write operation to create a modified verify cycle; then programming a first data into the memory array using the write operation that uses the modified verify cycle. Methods additionally include receiving a second temperature reading of the memory array, the second temperature reading includes a second temperature value; determining the second temperature value is below a second threshold, in response, decreasing the duration of a verify cycle of a verify cycle to create a second verify cycle, where the second verify cycle is shorter than the modified verify cycle; and then programming a second data into the memory array using the write operation that uses the second verify cycle.
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Piyush Dak, Mohan Dunga, Chao Qin, Muhammad Masuduzzaman, Xiang Yang
  • Patent number: 10312342
    Abstract: An electrical circuit comprising at least two negative capacitance insulators connected in series, one of the two negative capacitance insulators is biased to generate a negative capacitance. One of the negative capacitance insulators may include an air-gap which is part of a nanoelectromechnical system (NEMS) device and the second negative capacitance insulator includes a ferroelectric material. Both of the negative capacitance insulators may be located between the channel and gate of a field effect transistor. The NEMS device may include a movable electrode, a dielectric and a fixed electrode and arranged so that the movable electrode is attached to at least two points and spaced apart from the dielectric and fixed electrode, and the ferroelectric capacitor is electrically connected to either of the electrodes.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: June 4, 2019
    Assignee: Purdue Research Foundation
    Inventors: Muhammad Ashraful Alam, Muhammad Masuduzzaman, Ankit Jain
  • Patent number: 10217520
    Abstract: In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. In some cases, the duty cycle is a function of programming data of a memory cell such as an assigned data state or a programming speed category. The duty cycle could also be a function of a programming phase or other criterion. The duty cycle can be varied by modifying the duration and separation of the pulses of the waveform or by pulse counting, in which a specified number of pulses are passed in a time period.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: February 26, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Muhammad Masuduzzaman, Deepanshu Dutta, Jong Yuh
  • Patent number: 10014063
    Abstract: Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum verify scheme is implemented on a per-group basis for groups of adjacent memory cells at different heights in a 3D memory device. In another approach, an optimum verify scheme is implemented on a per-layer basis for sets of memory cells at a common height or word line layer in a 3D memory device.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: July 3, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Huai-Yuan Tseng, Deepanshu Dutta, Tai-Yuan Tseng, Grishma Shah, Muhammad Masuduzzaman
  • Publication number: 20180158531
    Abstract: In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. In some cases, the duty cycle is a function of programming data of a memory cell such as an assigned data state or a programming speed category. The duty cycle could also be a function of a programming phase or other criterion. The duty cycle can be varied by modifying the duration and separation of the pulses of the waveform or by pulse counting, in which a specified number of pulses are passed in a time period.
    Type: Application
    Filed: August 24, 2017
    Publication date: June 7, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Muhammad Masuduzzaman, Deepanshu Dutta, Jong Yuh
  • Publication number: 20180012972
    Abstract: An electrical circuit comprising at least two negative capacitance insulators connected in series, one of the two negative capacitance insulators is biased to generate a negative capacitance. One of the negative capacitance insulators may include an air-gap which is part of a nanoelectromechnical system (NEMS) device and the second negative capacitance insulator includes a ferroelectric material. Both of the negative capacitance insulators may be located between the channel and gate of a field effect transistor. The NEMS device may include a movable electrode, a dielectric and a fixed electrode and arranged so that the movable electrode is attached to at least two points and spaced apart from the dielectric and fixed electrode, and the ferroelectric capacitor is electrically connected to either of the electrodes.
    Type: Application
    Filed: September 5, 2017
    Publication date: January 11, 2018
    Applicant: Purdue Research Foundation
    Inventors: Muhammad Ashraful Alam, Muhammad Masuduzzaman, Ankit Jain
  • Patent number: 9842657
    Abstract: Multi-state programming of non-volatile memory cells, where cells being programmed to different target states are programmed concurrently, is performed by modulating the program speed of each state using a controlled amount of state-dependent weak boosting in their respective channels. In one example, the channel boosting is controlled by using a multi-stair word line ramp in conjunction with raising of the voltage on bit lines at a time based on the corresponding memory cell's target state.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: December 12, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Deepanshu Dutta, Xiaochang Miao, Muhammad Masuduzzaman
  • Patent number: 9779832
    Abstract: In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. In some cases, the duty cycle is a function of programming data of a memory cell such as an assigned data state or a programming speed category. The duty cycle could also be a function of a programming phase or other criterion. The duty cycle can be varied by modifying the duration and separation of the pulses of the waveform or by pulse counting, in which a specified number of pulses are passed in a time period.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: October 3, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Muhammad Masuduzzaman, Deepanshu Dutta, Jong Yuh
  • Patent number: 9755041
    Abstract: An electrical circuit comprising at least two negative capacitance insulators connected in series, one of the two negative capacitance insulators is biased to generate a negative capacitance. One of the negative capacitance insulators may include an air-gap which is part of a nanoelectromechnical system (NEMS) device and the second negative capacitance insulator includes a ferroelectric material. Both of the negative capacitance insulators may be located between the channel and gate of a field effect transistor. The NEMS device may include a movable electrode, a dielectric and a fixed electrode and arranged so that the movable electrode is attached to at least two points and spaced apart from the dielectric and fixed electrode, and the ferroelectric capacitor is electrically connected to either of the electrodes.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: September 5, 2017
    Assignee: PURDUE RESEARCH FOUNDATION
    Inventors: Muhammad Ashraful Alam, Muhammad Masuduzzaman, Ankit Jain
  • Patent number: 9711211
    Abstract: Based on performance during programming, the non-volatile memory cells are classified as fast programming memory cells and slow programming memory cells (or other classifications). At a separate time for each programmed state, threshold voltage distributions are compacted based on the classification.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: July 18, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Muhammad Masuduzzaman, Tai-Yuan Tseng, Huai-Yuan Tseng, Deepanshu Dutta
  • Publication number: 20170125087
    Abstract: Based on performance during programming, the non-volatile memory cells are classified as fast programming memory cells and slow programming memory cells (or other classifications). At a separate time for each programmed state, threshold voltage distributions are compacted based on the classification.
    Type: Application
    Filed: October 29, 2015
    Publication date: May 4, 2017
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Muhammad Masuduzzaman, Tai-Yuan Tseng, Huai-Yuan Tseng, Deepanshu Dutta
  • Publication number: 20170125117
    Abstract: Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum verify scheme is implemented on a per-group basis for groups of adjacent memory cells at different heights in a 3D memory device. In another approach, an optimum verify scheme is implemented on a per-layer basis for sets of memory cells at a common height or word line layer in a 3D memory device.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Huai-Yuan Tseng, Deepanshu Dutta, Tai-Yuan Tseng, Grishma Shah, Muhammad Masuduzzaman
  • Publication number: 20160379702
    Abstract: A method and apparatus for increasing the lifetime of ferroelectric devices is presented. The method includes applying a waveform to the input pulse to increase the rise or fall time of the pulse. The waveform may comprise a ramp, a step, or combinations of both. The waveform may be symmetrical with respect to the rising and falling edges of the pulses. A temperature control device may also be operatively connected to increase the temperature of the device to increase lifetime. In other embodiments, a resistance may be operatively connected in series with the ferroelectric device to increase lifetime.
    Type: Application
    Filed: September 12, 2016
    Publication date: December 29, 2016
    Applicant: Purdue Research Foundation
    Inventors: Muhammad Ashraful Alam, Muhammad Masuduzzaman
  • Publication number: 20160207761
    Abstract: An electrical circuit comprising at least two negative capacitance insulators connected in series, one of the two negative capacitance insulators is biased to generate a negative capacitance. One of the negative capacitance insulators may include an air-gap which is part of a nanoelectromechnical system (NEMS) device and the second negative capacitance insulator includes a ferroelectric material. Both of the negative capacitance insulators may be located between the channel and gate of a field effect transistor. The NEMS device may include a movable electrode, a dielectric and a fixed electrode and arranged so that the movable electrode is attached to at least two points and spaced apart from the dielectric and fixed electrode, and the ferroelectric capacitor is electrically connected to either of the electrodes.
    Type: Application
    Filed: April 30, 2015
    Publication date: July 21, 2016
    Applicant: Purdue Research Foundation
    Inventors: Muhammad Ashraful Alam, Muhammad Masuduzzaman, Ankit Jain
  • Publication number: 20150124514
    Abstract: A method and apparatus for increasing the lifetime of ferroelectric devices is presented. The method includes applying a waveform to the input pulse to increase the rise or fall time of the pulse. The waveform may comprise a ramp, a step, or combinations of both. The waveform may be symmetrical with respect to the rising and falling edges of the pulses. A temperature control device may also be operatively connected to increase the temperature of the device to increase lifetime. In other embodiments, a resistance may be operatively connected in series with the ferroelectric device to increase lifetime.
    Type: Application
    Filed: November 5, 2014
    Publication date: May 7, 2015
    Applicant: PURDUE RESEARCH FOUNDATION
    Inventors: Muhammad Ashraful Alam, Muhammad Masuduzzaman