Patents by Inventor Muhammad Masuduzzaman
Muhammad Masuduzzaman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210391012Abstract: A storage device may be configured to determine data states for a first set of memory cells, of an array of memory cells, that are part of a logical N?1 neighboring word line that is adjacent to a selected word line. The storage device may be further configured to determine a program voltage configuration based on the data states. The storage device may be further configured to determine, using the program voltage configuration, a program operation on the selected word line to iteratively program respective memory cells, of a second set of memory cells that are part of the selected word line. Determining the data states, determining the program voltage configuration, and performing the program operation may be repeated until a program stop condition is satisfied.Type: ApplicationFiled: June 12, 2020Publication date: December 16, 2021Applicant: SanDisk Technologies LLCInventors: Muhammad Masuduzzaman, Deepanshu Dutta
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Publication number: 20210391025Abstract: A method comprises determining a verify voltage for a next iteration of a verify operation to be performed on memory cells a first set of memory cells of a selected word line, and determining data states for a second set of memory cells of at least one neighboring word line. The method further comprises determining, based on the data states, a verify voltage configuration that includes bit line voltage biases or sense times, and performing the next iteration of the verify operation on the selected word line by using the verify voltage configuration to iteratively verify whether respective memory cells, of the second set of memory cells, have threshold voltages above the verify voltage, wherein determining the data states, determining the verify voltage configuration, and performing the next iteration are to be repeated until a program stop condition is satisfied.Type: ApplicationFiled: June 12, 2020Publication date: December 16, 2021Applicant: San Disk Technologies LLCInventors: Muhammad Masuduzzaman, Deepanshu Dutta
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Patent number: 11139038Abstract: A method for programming a target memory cell of a memory array of a non-volatile memory system, the method comprising performing a read operation of one or more memory cells neighboring a target memory cell, thereby determining a data pattern of the one or more neighboring memory cells, storing the data pattern and, during a program operation of the target memory cell, adjusting a verify voltage level according to the stored data pattern of the one or more neighboring memory cells.Type: GrantFiled: June 17, 2020Date of Patent: October 5, 2021Assignee: SanDisk Technologies LLCInventors: Muhammad Masuduzzaman, Deepanshu Dutta, Huai-Yuan Tseng
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Patent number: 11081184Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the first memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.Type: GrantFiled: December 3, 2019Date of Patent: August 3, 2021Assignee: SanDisk Technologies LLCInventors: Zhiping Zhang, Muhammad Masuduzzaman, Huai-Yuan Tseng, Dengtao Zhao, Deepanshu Dutta
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Publication number: 20210134372Abstract: A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.Type: ApplicationFiled: November 6, 2019Publication date: May 6, 2021Applicant: SanDisk Technologies LLCInventors: Zhiping Zhang, Muhammad Masuduzzaman, Huai-Yuan Tseng, Peng Zhang, Dengtao Zhao, Deepanshu Dutta
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Publication number: 20210134370Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the first memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.Type: ApplicationFiled: December 3, 2019Publication date: May 6, 2021Applicant: SanDisk Technologies LLCInventors: Zhiping Zhang, Muhammad Masuduzzaman, Huai-Yuan Tseng, Dengtao Zhao, Deepanshu Dutta
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Publication number: 20210134369Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the fist memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.Type: ApplicationFiled: October 30, 2019Publication date: May 6, 2021Applicant: SanDisk Technologies LLCInventors: Zhiping Zhang, Muhammad Masuduzzaman, Huai-Yuan Tseng, Dengtao Zhao, Deepanshu Dutta
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Patent number: 10984876Abstract: Various methods include receiving, by a controller, a temperature reading of a memory array, the temperature reading includes a temperature value; determining the temperature value is below a first threshold; in response, modifying a duration of a verify cycle of a write operation to create a modified verify cycle; then programming a first data into the memory array using the write operation that uses the modified verify cycle. Methods additionally include receiving a second temperature reading of the memory array, the second temperature reading includes a second temperature value; determining the second temperature value is below a second threshold, in response, decreasing the duration of a verify cycle of a verify cycle to create a second verify cycle, where the second verify cycle is shorter than the modified verify cycle; and then programming a second data into the memory array using the write operation that uses the second verify cycle.Type: GrantFiled: June 19, 2019Date of Patent: April 20, 2021Assignee: SanDiskTechnologies LLCInventors: Piyush Dak, Mohan Dunga, Chao Qin, Muhammad Masuduzzaman, Xiang Yang
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Publication number: 20200402594Abstract: Various methods include receiving, by a controller, a temperature reading of a memory array, the temperature reading includes a temperature value; determining the temperature value is below a first threshold; in response, modifying a duration of a verify cycle of a write operation to create a modified verify cycle; then programming a first data into the memory array using the write operation that uses the modified verify cycle. Methods additionally include receiving a second temperature reading of the memory array, the second temperature reading includes a second temperature value; determining the second temperature value is below a second threshold, in response, decreasing the duration of a verify cycle of a verify cycle to create a second verify cycle, where the second verify cycle is shorter than the modified verify cycle; and then programming a second data into the memory array using the write operation that uses the second verify cycle.Type: ApplicationFiled: June 19, 2019Publication date: December 24, 2020Applicant: SanDisk Technologies LLCInventors: Piyush Dak, Mohan Dunga, Chao Qin, Muhammad Masuduzzaman, Xiang Yang
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Patent number: 10312342Abstract: An electrical circuit comprising at least two negative capacitance insulators connected in series, one of the two negative capacitance insulators is biased to generate a negative capacitance. One of the negative capacitance insulators may include an air-gap which is part of a nanoelectromechnical system (NEMS) device and the second negative capacitance insulator includes a ferroelectric material. Both of the negative capacitance insulators may be located between the channel and gate of a field effect transistor. The NEMS device may include a movable electrode, a dielectric and a fixed electrode and arranged so that the movable electrode is attached to at least two points and spaced apart from the dielectric and fixed electrode, and the ferroelectric capacitor is electrically connected to either of the electrodes.Type: GrantFiled: September 5, 2017Date of Patent: June 4, 2019Assignee: Purdue Research FoundationInventors: Muhammad Ashraful Alam, Muhammad Masuduzzaman, Ankit Jain
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Patent number: 10217520Abstract: In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. In some cases, the duty cycle is a function of programming data of a memory cell such as an assigned data state or a programming speed category. The duty cycle could also be a function of a programming phase or other criterion. The duty cycle can be varied by modifying the duration and separation of the pulses of the waveform or by pulse counting, in which a specified number of pulses are passed in a time period.Type: GrantFiled: August 24, 2017Date of Patent: February 26, 2019Assignee: SanDisk Technologies LLCInventors: Muhammad Masuduzzaman, Deepanshu Dutta, Jong Yuh
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Patent number: 10014063Abstract: Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum verify scheme is implemented on a per-group basis for groups of adjacent memory cells at different heights in a 3D memory device. In another approach, an optimum verify scheme is implemented on a per-layer basis for sets of memory cells at a common height or word line layer in a 3D memory device.Type: GrantFiled: October 30, 2015Date of Patent: July 3, 2018Assignee: SanDisk Technologies LLCInventors: Huai-Yuan Tseng, Deepanshu Dutta, Tai-Yuan Tseng, Grishma Shah, Muhammad Masuduzzaman
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Publication number: 20180158531Abstract: In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. In some cases, the duty cycle is a function of programming data of a memory cell such as an assigned data state or a programming speed category. The duty cycle could also be a function of a programming phase or other criterion. The duty cycle can be varied by modifying the duration and separation of the pulses of the waveform or by pulse counting, in which a specified number of pulses are passed in a time period.Type: ApplicationFiled: August 24, 2017Publication date: June 7, 2018Applicant: SanDisk Technologies LLCInventors: Muhammad Masuduzzaman, Deepanshu Dutta, Jong Yuh
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Publication number: 20180012972Abstract: An electrical circuit comprising at least two negative capacitance insulators connected in series, one of the two negative capacitance insulators is biased to generate a negative capacitance. One of the negative capacitance insulators may include an air-gap which is part of a nanoelectromechnical system (NEMS) device and the second negative capacitance insulator includes a ferroelectric material. Both of the negative capacitance insulators may be located between the channel and gate of a field effect transistor. The NEMS device may include a movable electrode, a dielectric and a fixed electrode and arranged so that the movable electrode is attached to at least two points and spaced apart from the dielectric and fixed electrode, and the ferroelectric capacitor is electrically connected to either of the electrodes.Type: ApplicationFiled: September 5, 2017Publication date: January 11, 2018Applicant: Purdue Research FoundationInventors: Muhammad Ashraful Alam, Muhammad Masuduzzaman, Ankit Jain
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Patent number: 9842657Abstract: Multi-state programming of non-volatile memory cells, where cells being programmed to different target states are programmed concurrently, is performed by modulating the program speed of each state using a controlled amount of state-dependent weak boosting in their respective channels. In one example, the channel boosting is controlled by using a multi-stair word line ramp in conjunction with raising of the voltage on bit lines at a time based on the corresponding memory cell's target state.Type: GrantFiled: May 18, 2017Date of Patent: December 12, 2017Assignee: SanDisk Technologies LLCInventors: Deepanshu Dutta, Xiaochang Miao, Muhammad Masuduzzaman
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Patent number: 9779832Abstract: In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. In some cases, the duty cycle is a function of programming data of a memory cell such as an assigned data state or a programming speed category. The duty cycle could also be a function of a programming phase or other criterion. The duty cycle can be varied by modifying the duration and separation of the pulses of the waveform or by pulse counting, in which a specified number of pulses are passed in a time period.Type: GrantFiled: December 7, 2016Date of Patent: October 3, 2017Assignee: SanDisk Technologies LLCInventors: Muhammad Masuduzzaman, Deepanshu Dutta, Jong Yuh
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Patent number: 9755041Abstract: An electrical circuit comprising at least two negative capacitance insulators connected in series, one of the two negative capacitance insulators is biased to generate a negative capacitance. One of the negative capacitance insulators may include an air-gap which is part of a nanoelectromechnical system (NEMS) device and the second negative capacitance insulator includes a ferroelectric material. Both of the negative capacitance insulators may be located between the channel and gate of a field effect transistor. The NEMS device may include a movable electrode, a dielectric and a fixed electrode and arranged so that the movable electrode is attached to at least two points and spaced apart from the dielectric and fixed electrode, and the ferroelectric capacitor is electrically connected to either of the electrodes.Type: GrantFiled: April 30, 2015Date of Patent: September 5, 2017Assignee: PURDUE RESEARCH FOUNDATIONInventors: Muhammad Ashraful Alam, Muhammad Masuduzzaman, Ankit Jain
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Patent number: 9711211Abstract: Based on performance during programming, the non-volatile memory cells are classified as fast programming memory cells and slow programming memory cells (or other classifications). At a separate time for each programmed state, threshold voltage distributions are compacted based on the classification.Type: GrantFiled: October 29, 2015Date of Patent: July 18, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Muhammad Masuduzzaman, Tai-Yuan Tseng, Huai-Yuan Tseng, Deepanshu Dutta
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Publication number: 20170125117Abstract: Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum verify scheme is implemented on a per-group basis for groups of adjacent memory cells at different heights in a 3D memory device. In another approach, an optimum verify scheme is implemented on a per-layer basis for sets of memory cells at a common height or word line layer in a 3D memory device.Type: ApplicationFiled: October 30, 2015Publication date: May 4, 2017Applicant: SANDISK TECHNOLOGIES INC.Inventors: Huai-Yuan Tseng, Deepanshu Dutta, Tai-Yuan Tseng, Grishma Shah, Muhammad Masuduzzaman
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Publication number: 20170125087Abstract: Based on performance during programming, the non-volatile memory cells are classified as fast programming memory cells and slow programming memory cells (or other classifications). At a separate time for each programmed state, threshold voltage distributions are compacted based on the classification.Type: ApplicationFiled: October 29, 2015Publication date: May 4, 2017Applicant: SANDISK TECHNOLOGIES INC.Inventors: Muhammad Masuduzzaman, Tai-Yuan Tseng, Huai-Yuan Tseng, Deepanshu Dutta