Patents by Inventor Muhammad TAHER
Muhammad TAHER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230305742Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.Type: ApplicationFiled: June 1, 2023Publication date: September 28, 2023Applicant: Intel CorporationInventors: Ahmad YASIN, Michael CHYNOWETH, Rajshree CHABUKSWAR, Muhammad TAHER
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Patent number: 11693588Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.Type: GrantFiled: April 21, 2020Date of Patent: July 4, 2023Assignee: Intel CorporationInventors: Ahmad Yasin, Michael Chynoweth, Rajshree Chabukswar, Muhammad Taher
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Patent number: 11544062Abstract: An apparatus and method for pairing store operations. For example, one embodiment of a processor comprises: a grouping eligibility checker to evaluate a plurality of store instructions based on a set of grouping rules to determine whether two or more of the plurality of store instructions are eligible for grouping; and a dispatcher to simultaneously dispatch a first group of store instructions of the plurality of store instructions determined to be eligible for grouping by the grouping eligibility checker.Type: GrantFiled: March 28, 2020Date of Patent: January 3, 2023Assignee: Intel CorporationInventors: Raanan Sade, Igor Yanover, Stanislav Shwartsman, Muhammad Taher, David Zysman, Liron Zur, Yiftach Gilad
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Publication number: 20210096860Abstract: An apparatus and method for pairing store operations. For example, one embodiment of a processor comprises: a grouping eligibility checker to evaluate a plurality of store instructions based on a set of grouping rules to determine whether two or more of the plurality of store instructions are eligible for grouping; and a dispatcher to simultaneously dispatch a first group of store instructions of the plurality of store instructions determined to be eligible for grouping by the grouping eligibility checker.Type: ApplicationFiled: March 28, 2020Publication date: April 1, 2021Inventors: Raanan SADE, Igor YANOVER, Stanislav SHWARTSMAN, Muhammad TAHER, David ZYSMAN, Liron ZUR, Yiftach GILAD
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Publication number: 20200249866Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.Type: ApplicationFiled: April 21, 2020Publication date: August 6, 2020Inventors: Ahmad YASIN, Michael CHYNOWETH, Rajshree CHABUKSWAR, Muhammad TAHER
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Patent number: 10649688Abstract: A processor includes a memory subsystem having a first memory subunit that includes a status register and an execution engine unit coupled to the memory subsystem. The execution engine unit is to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit stores a piece of information, related to a status of the load operation, in the status register. Responsive to detection of retirement of the load operation, the first memory subunit is to store the piece of information from the status register into a particular field of a record of a memory buffer, wherein the particular field is associated with the first memory subunit.Type: GrantFiled: November 1, 2018Date of Patent: May 12, 2020Assignee: Intel CorporationInventors: Ahmad Yasin, Michael Chynoweth, Rajshree Chabukswar, Muhammad Taher
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Publication number: 20200142629Abstract: A processor includes a memory subsystem having a first memory subunit that includes a status register and an execution engine unit coupled to the memory subsystem. The execution engine unit is to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit stores a piece of information, related to a status of the load operation, in the status register. Responsive to detection of retirement of the load operation, the first memory subunit is to store the piece of information from the status register into a particular field of a record of a memory buffer, wherein the particular field is associated with the first memory subunit.Type: ApplicationFiled: November 1, 2018Publication date: May 7, 2020Inventors: Ahmad YASIN, Michael CHYNOWETH, Rajshree CHABUKSWAR, Muhammad TAHER
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Patent number: 10545462Abstract: A time-to-voltage converter (TVC) that can include a timer integrated circuit (IC), and a charging circuit including a constant current source and a capacitor connected in series. The capacitor can be connected to a discharge pin of the timer IC. The TVC can further include a trigger circuit and a reset circuit to receive a start signal and a stop signal, respectively, from an input line, and accordingly generate a trigger signal or a reset signal to trigger or reset the timer IC. A switch can be configured to, under control of an output signal of the timer IC, connect the input line with the reset circuit. A voltage across the capacitor when the timer IC is reset indicates a time interval corresponding to the start and stop signals.Type: GrantFiled: April 26, 2019Date of Patent: January 28, 2020Assignee: King Fahd University of Petroleum and MineralsInventor: Muhammad Taher Abuelma'Atti
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Patent number: 10528010Abstract: A time-to-voltage converter (TVC) including a 555 timer integrated circuit (IC), and a charging circuit including a constant current source and a capacitor connected in series. The capacitor can be connected to a discharge pin of the 555 timer IC. The TVC can further include a trigger circuit and a reset circuit to receive a start signal and a stop signal, respectively, from an input line, and accordingly generate a trigger signal or a reset signal to trigger or reset the 555 timer IC. A switch can be configured to, under control of an output signal of the 555 timer IC, connect the input line with the reset circuit. A voltage across the capacitor when the 555 timer IC is reset indicates a time interval corresponding to the start and stop signals.Type: GrantFiled: April 26, 2019Date of Patent: January 7, 2020Assignee: King Fahd University of Petroleum and MineralsInventor: Muhammad Taher Abuelma'Atti
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Publication number: 20190286065Abstract: A time-to-voltage converter (TVC) including a 555 timer integrated circuit (IC), and a charging circuit including a constant current source and a capacitor connected in series. The capacitor can be connected to a discharge pin of the 555 timer IC. The TVC can further include a trigger circuit and a reset circuit to receive a start signal and a stop signal, respectively, from an input line, and accordingly generate a trigger signal or a reset signal to trigger or reset the 555 timer IC. A switch can be configured to, under control of an output signal of the 555 timer IC, connect the input line with the reset circuit. A voltage across the capacitor when the 555 timer IC is reset indicates a time interval corresponding to the start and stop signals.Type: ApplicationFiled: April 26, 2019Publication date: September 19, 2019Applicant: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALSInventor: Muhammad Taher ABUELMA'ATTI
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Publication number: 20190286066Abstract: Aspects of the disclosure provide a time-to-voltage converter (TVC). The TVC can include a 555 timer integrated circuit (IC), and a charging circuit including a constant current source and a capacitor connected in series. The capacitor can be connected to a discharge pin of the 555 timer IC. The TVC can further include a trigger circuit and a reset circuit to receive a start signal and a stop signal, respectively, from an input line, and accordingly generate a trigger signal or a reset signal to trigger or reset the 555 timer IC. A switch can be configured to, under control of an output signal of the 555 timer IC, connect the input line with the reset circuit. A voltage across the capacitor when the 555 timer IC is reset indicates a time interval corresponding to the start and stop signals.Type: ApplicationFiled: April 26, 2019Publication date: September 19, 2019Applicant: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALSInventor: Muhammad Taher ABUELMA'ATTI
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Patent number: 10324420Abstract: A time-to-voltage converter (TVC) that includes a 555 timer integrated circuit (IC), and a charging circuit including a constant current source and a capacitor connected in series. The capacitor can be connected to a discharge pin of the 555 timer IC. The TVC can further include a trigger circuit and a reset circuit to receive a start signal and a stop signal, respectively, from an input line, and accordingly generate a trigger signal or a reset signal to trigger or reset the 555 timer IC. A switch can be configured to, under control of an output signal of the 555 timer IC, connect the input line with the reset circuit. A voltage across the capacitor when the 555 timer IC is reset indicates a time interval corresponding to the start and stop signals.Type: GrantFiled: March 19, 2018Date of Patent: June 18, 2019Assignee: King Fahd University of Petroleum and MineralsInventor: Muhammad Taher Abuelma'atti
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Patent number: 9837986Abstract: The floating immittance emulator is presented in four embodiments in which four new topologies for emulating floating immittance functions are detailed. Each circuit uses three current-feedback operational-amplifiers (CFOAs) and three passive elements. The present topologies can emulate lossless and lossy floating inductances; capacitance, resistance, and inductance multipliers; and frequency-dependent positive and negative resistances.Type: GrantFiled: October 28, 2016Date of Patent: December 5, 2017Assignee: King Fahd University of Petroleum and MineralsInventors: Muhammad Taher Abuelma'atti, Sagar Kumar Dhar
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Patent number: 9837987Abstract: The floating immittance emulator is presented in four embodiments in which four new topologies for emulating floating immittance functions are detailed. Each circuit uses three current-feedback operational-amplifiers (CFOAs) and three passive elements. The present topologies can emulate lossless and lossy floating inductances; capacitance, resistance, and inductance multipliers; and frequency-dependent positive and negative resistances.Type: GrantFiled: October 28, 2016Date of Patent: December 5, 2017Assignee: King Fahd University of Petroleum and MineralsInventors: Muhammad Taher Abuelma'atti, Sagar Kumar Dhar
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Patent number: 9837985Abstract: The floating immittance emulator is presented in four embodiments in which four new topologies for emulating floating immittance functions are detailed. Each circuit uses three current-feedback operational-amplifiers (CFOAs) and three passive elements. The present topologies can emulate lossless and lossy floating inductances; capacitance, resistance, and inductance multipliers; and frequency-dependent positive and negative resistances.Type: GrantFiled: October 28, 2016Date of Patent: December 5, 2017Assignee: King Fahd University of Petroleum and MineralsInventors: Muhammad Taher Abuelma'atti, Sagar Kumar Dhar
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Publication number: 20170149414Abstract: The floating immittance emulator is presented in four embodiments in which four new topologies for emulating floating immittance functions are detailed. Each circuit uses three current-feedback operational-amplifiers (CFOAs) and three passive elements. The present topologies can emulate lossless and lossy floating inductances; capacitance, resistance, and inductance multipliers; and frequency-dependent positive and negative resistances.Type: ApplicationFiled: October 28, 2016Publication date: May 25, 2017Inventors: Muhammad Taher Abuelma'atti, Sagar Kumar Dhar
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Publication number: 20170149413Abstract: The floating immittance emulator is presented in four embodiments in which four new topologies for emulating floating immittance functions are detailed. Each circuit uses three current-feedback operational-amplifiers (CFOAs) and three passive elements. The present topologies can emulate lossless and lossy floating inductances; capacitance, resistance, and inductance multipliers; and frequency-dependent positive and negative resistances.Type: ApplicationFiled: October 28, 2016Publication date: May 25, 2017Inventors: Muhammad Taher ABUELMA'ATTI, Sagar Kumar DHAR
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Publication number: 20170149415Abstract: The floating immittance emulator is presented in four embodiments in which four new topologies for emulating floating immittance functions are detailed. Each circuit uses three current-feedback operational-amplifiers (CFOAs) and three passive elements. The present topologies can emulate lossless and lossy floating inductances; capacitance, resistance, and inductance multipliers; and frequency-dependent positive and negative resistances.Type: ApplicationFiled: October 28, 2016Publication date: May 25, 2017Inventors: MUHAMMAD TAHER ABUELMA'ATTI, SAGAR KUMAR DHAR
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Patent number: 9619596Abstract: The floating memristor emulator is based on a circuit implementation that uses grounded capacitors and CFOAs in addition to combinations of diodes and resistors to provide the required nonlinearity and time constants. This circuit results in low power consumption, cost reduction and ease of implementation because it avoids the use of multipliers, ADCs and RDACs. The present circuit is used in an FM demodulator, which exploits the frequency-dependence of the memristance. Successful use in the FM demodulator confirmed the functionality of the present floating memristor emulator circuit.Type: GrantFiled: June 23, 2015Date of Patent: April 11, 2017Assignee: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALSInventors: Muhammad Taher Abuelma'atti, Zainulabideen Jamal Khalifa
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Patent number: 9553562Abstract: The compact C-multiplier includes four MOSFETs operating in the subthreshold region using the translinear principle. The multiplier is controllable to meet designer requirements. A Tanner Tspice simulator is used to confirm the functionality of the design in 0.13 pm CMOS Technology. The circuit operates from a ±0.75 supply voltage. Simulation results indicate that the multiplication factor is large compared to existing designs.Type: GrantFiled: May 31, 2016Date of Patent: January 24, 2017Assignee: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALSInventors: Munir A. Al-Absi, Eyas Saleh Al-Suhaibani, Muhammad Taher Abuelma'atti