Abstract: A method is provided, comprising: (i) receiving, at a system, from an autonomous vehicle: (a) sensor data captured by a sensor of the vehicle, and (b) output data generated based on environmental data captured by one or more sensors of the vehicle and used by a planning component to navigate in an environment, (ii) causing one or more displays to display at least one of: a representation of the sensor data, or a model of the environment based on the output data, (iii) determining a location of a feature within the sensor data or the model, (iv) causing the one or more displays to display an indication of the feature at a position corresponding to the location, (v) receiving, at the system, user input, and (vi) sending, by the system to the vehicle, data based on the user input to cause the vehicle to take an action.

Abstract: Aspects of the subject disclosure may include, for example: building a computer-usable model; performing automated testing on the computer-usable model to determine whether the computer-usable model successfully handles a plurality of test scenarios; performing fault injection by injecting a plurality of faults into the computer-usable model to determine whether the computer-usable model successfully handles the plurality of faults, and facilitating deployment of the computer-usable model. Other aspects of the subject disclosure may include, for example: the deployed computer-usable model detecting and/or experiencing deviations, inconsistencies and/or anomalies; and activating one or more backup methods in response to the deployed computer-usable model detecting and/or experiencing deviations, inconsistencies and/or anomalies. The one or more backup methods can be implemented in a preferred order (e.g., depending upon the type of the deviations, inconsistencies and/or anomalies).

Abstract: There is provided a data processing apparatus in which decode circuitry receives a memory copy instruction containing an indication of a source area of memory, an indication of a destination area of memory, and an indication of a remaining copy length. In response to receiving the memory copy instruction, the decode circuitry generates at least one active memory copy operation or a null memory copy operation. The active memory copy operation causes one or more execution units to perform a memory copy from part of the source area of memory to part of the destination area of memory and the null memory copy operation leaves the destination area of memory unmodified.

Abstract: A computer implemented method is provided. The method, comprises: receiving from an autonomous vehicle sensor data, wherein the sensor data is indicative of an environment in which the vehicle is currently located or was previously located. The method further comprises receiving or determining additional data associated with at least one of: the sensor data, the vehicle, or the environment, wherein the additional data is different from the sensor data. The method further comprises displaying, on a display, an output comprising a representation of the sensor data. The method further comprises determining, based at least in part on the additional data, a reliability metric, the reliability metric being indicative of how reliable the sensor data is at representing the environment in which the vehicle is located at a current time. The method further comprises causing the output on the display to be based at least in part on the reliability metric.

Abstract: A data processing apparatus is provided that comprises rename circuitry for performing a register rename stage of a pipeline in respect of a stream of operations. Move elimination circuitry performs a move elimination operation on the stream of operations in which a move operation is eliminated and the register rename stage performs an adjustment of an identity of registers in the stream of operations to compensate for the move operation being eliminated and demotion circuitry reverses or inhibits the adjustment in response to one or more conditions being met.

Abstract: A system on chip includes a secure processing unit (SPU), an artificial intelligence/machine learning accelerator (AI/ML accelerator), a memory inline cypher engine, and a central processing unit (CPU). The SPU is used to store biometrics of users. The AI/ML accelerator is used to process images, and analyze the biometrics of users. The AI/ML accelerator includes a micro control unit (MCU) for intelligently linking access identifications (IDs) to version numbers (VNs). The inline cypher engine is coupled to the AI/ML accelerator and the SPU for receiving a register file from the MCU, encrypting data received from the AI/ML accelerator, and comparing the biometrics of the users received from the SPU with the data. The CPU is coupled to the SPU and the AI/ML accelerator for controlling the SPU and the AI/ML accelerator.

Abstract: Systems and methods for disengaging or engaging autonomy remotely are provided. The autonomous vehicle may receive a request from a remote computing system associated with a remote operator. The request may require the autonomous vehicle to disengage, engage, or re-engage autonomy. The autonomous vehicle may determine whether the request is valid, and whether certain safety criteria are met. Upon determining that the request is valid and safety criteria are met, the autonomous vehicle may process the request and cause the autonomous vehicle to enter the desired state. The autonomous vehicle may send a message to the remote computing system, indicating whether or not the autonomous vehicle has entered the desired state.

Abstract: A system on chip includes a secure processing unit (SPU), an artificial intelligence/machine learning accelerator (AI/ML accelerator), a memory inline cypher engine, and a central processing unit (CPU). The SPU is used to store biometrics of users. The AI/ML accelerator is used to process images, and analyze the biometrics of users. The AI/ML accelerator includes a micro control unit (MCU) for intelligently linking access identifications (IDs) to version numbers (VNs). The inline cypher engine is coupled to the AI/ML accelerator and the SPU for receiving a register file from the MCU, encrypting data received from the AI/ML accelerator, and comparing the biometrics of the users received from the SPU with the data. The CPU is coupled to the SPU and the AI/ML accelerator for controlling the SPU and the AI/ML accelerator.

Abstract: Image data of a first image in a sequence of images is processed using an artificial neural network (ANN) to generate output image data indicative of an alignment of the first image with a second image in the sequence. The ANN is trained using outputs of an alignment pipeline configured to perform alignment of images. The alignment pipeline is configured to determine flow vectors representing optical flow between images, and perform an image transformation using the flow vectors to align the images. The ANN is trained to emulate a result derivable using the alignment pipeline.

Abstract: Image data representing one or more images at a first resolution is received at a first artificial neural network (ANN). The image data is processed using the first ANN to generate upscaled image data representing the one or more images at a second, higher resolution. The first ANN is trained to perform image upscaling and is trained using first training image data representing one or more training images at the first resolution, the first training image data being at a first level of quality. The first ANN is also trained using features of a second ANN, wherein the second ANN is trained to perform image upscaling and is trained using second training image data representing one or more training images at the first resolution, the second training image data being at a second level of quality, higher than the first level of quality.

Abstract: There is provided a data processing apparatus in which decode circuitry receives a memory copy instruction containing an indication of a source area of memory, an indication of a destination area of memory, and an indication of a remaining copy length. In response to receiving the memory copy instruction, the decode circuitry generates at least one active memory copy operation or a null memory copy operation. The active memory copy operation causes one or more execution units to perform a memory copy from part of the source area of memory to part of the destination area of memory and the null memory copy operation leaves the destination area of memory unmodified.

Abstract: Aspects of the present disclosure relate an apparatus comprising fetch circuitry and instruction storage circuitry. The fetch circuitry is to fetch instructions for execution by execution circuitry. The instruction storage circuitry is to store temporary copies of fetched instructions. The fetch circuitry is configured to preferentially fetch instructions from the instruction storage circuitry. The instruction storage circuitry is configured to, responsive to a storage condition being met, begin storing copies of consecutive fetched instructions, the storage condition indicating a utility of a current fetched instruction; and to, responsive to determining that a number of said stored consecutive instructions has reached a storage threshold, cease storing copies of subsequent fetched instructions.

Abstract: Bearing steel comprising cubic boron nitride (c-BN) and/or nickel coated cBN spark plasma sintered at a temperature in the range of 850-1050° C. is disclosed. The tribological and corrosion resistance of the bearing steel improved with increasing the amount of c-BN. Further improvement in the properties was achieved with the incorporation of nickel coated c-BN, which caused a phase transition of the bearing steel from magnetic to non-magnetic phase accompanied by interdiffusion enhancement between the matrix and c-BN reinforcement.

Abstract: A data processing apparatus is provided that comprises rename circuitry for performing a register rename stage of a pipeline in respect of a stream of operations. Move elimination circuitry performs a move elimination operation on the stream of operations in which a move operation is eliminated and the register rename stage performs an adjustment of an identity of registers in the stream of operations to compensate for the move operation being eliminated and demotion circuitry reverses or inhibits the adjustment in response to one or more conditions being met.

Abstract: Heating of rubber products during processing produces odours which may be abated by commingling the rubber product with fabric softener. The fabric softener may be commingled with the rubber product via a dip tank filled with fabric softener solution, by applying fabric softener to the rubber product prior to heating/processing the rubber product, by injecting the fabric softener into an extruder that is heating/processing the rubber product, and by treating the by-product exiting the side stream of the extruder.

Abstract: A depth estimation device includes a difference map generating network and a depth transformation circuit. The difference map generating network generates, from a monocular input image and using a plurality of neural networks, a plurality of difference maps corresponding to a plurality of baselines. The plurality of difference maps includes a first difference map corresponding to a first baseline and a second difference map corresponding to a second baseline. The depth transformation circuit generates a depth map using one of the plurality of difference maps.

Abstract: A data processing apparatus is provided that includes global-history prediction circuitry that provides a prediction of an outcome of a given control flow instruction based on a result of execution of one or more previous control flow instructions. Correction circuitry provides a corrected prediction of the global-history prediction circuitry in respect of the given control flow instruction and cache circuitry, separate from the correction circuitry, stores the corrected prediction in respect of the given control flow instruction.

Abstract: An apparatus and method are provided for processing instructions fetched from memory. Decode circuitry is used to decode the fetched instructions in order to produce decoded instructions, and downstream circuitry then processes the decoded instructions in order to perform the operations specified by those decoded instructions. Dispatch circuitry is arranged to dispatch to the downstream circuitry up to N decoded instructions per dispatch cycle, and is arranged to determine, based on a given candidate sequence of decoded instructions being considered for dispatch in a given dispatch cycle, whether at least one resource conflict within the downstream circuitry would occur in the event that the given candidate sequence of decoded instructions is dispatched in the given dispatch cycle.

Abstract: Aspects of the present disclosure relate an apparatus comprising fetch circuitry and instruction storage circuitry. The fetch circuitry is to fetch instructions for execution by execution circuitry. The instruction storage circuitry is to store temporary copies of fetched instructions. The fetch circuitry is configured to preferentially fetch instructions from the instruction storage circuitry. The instruction storage circuitry is configured to, responsive to a storage condition being met, begin storing copies of consecutive fetched instructions, the storage condition indicating a utility of a current fetched instruction; and to, responsive to determining that a number of said stored consecutive instructions has reached a storage threshold, cease storing copies of subsequent fetched instructions.

Abstract: An apparatus comprises first-level and second-level set-associative caches each comprising the same number of sets of cache entries. Indexing circuitry generates, based on a lookup address, a set index identifying which set of the first-level set-associative cache or the second-level set-associative cache is a selected set of cache entries to be looked up for information associated with the lookup address. The indexing circuitry generates the set index using an indexing scheme which maps the lookup address to the same set index for both the first-level set-associative cache and the second-level set-associative cache. This can make migration of cached information between the cache levels more efficient, which can be particularly useful for caches with high access frequency, such as branch target buffers for a branch predictor.