Abstract: A high voltage semiconductor device having improved electrical raggedness and reduced cell pitch wherein, for an N- channel device, the P+ region (22') extends to the gate contact (28) and wherein the P+ region and the N+ source region (20') overlap efficiently so that the depth of the overlap portion (24') is at least as deep as the N+ source region (20').

Abstract: A lateral semiconductor device is disclosed having a semiconductor body of a first conductivity type, and a drift region having a second conductivity type opposite that of the first conductivity type and formed on a surface of the semiconductor body. A drain region formed in the drift region includes an end portion having a surface area including a predetermined surface radius of curvature and a first surface width; a transitional portion tapers from the first surface width to a second surface width; and a medial portion having the second surface width. A source region is formed in the drift region and spaced from the drain region.

Abstract: A semiconductor device comprising a semiconductor substrate with a base region, a collector region and an emitter region in a lateral arrangement. The base region having a first conductivity type, and the collector and emitter regions having a second conductivity type. A first conductor layer is patterned over the substrate with a base contact portion, a collector contact portion and an emitter contact portion, with the base contact portion, the collector contact portion and the emitter contact portion contacting the base region, the collector region and the emitter region, respectively. A second conductor layer is patterned over a portion of the base region and is electrically coupled to the emitter contact portion, whereby the second conductor layer functions as an electrostatic shield for the base region.

Abstract: A method of making a doubly-diffused MOS (DMOS) device that can tolerate higher drain dV/dt before latch-up occurs. At least some of the immediately adjacent multiple body regions in the DMOS device are interconnected at the corners thereof by the formation of P-conductivity regions. These regions reduce parasitic bipolar effects and facilitate collection of excess carriers in the device that causes latch-up under high dV/dt conditions and reduced avalanche energy tolerance.

Abstract: A semiconductor device (12) with reduced high voltage termination area and high breakdown voltage. The device comprises first and second field shield plates (46), (48). The first field shield plate (46) is disposed above a high voltage first impurity region (22) and a junction extension doped region (42) and is in contact with a conductive material (26) which comprises the high voltage terminal of the device (12). A second field shield plate (48) is disposed above a low voltage second impurity region (30) and the junction extension doped region (42) and is covered by an extended portion (35) of a low voltage source contact (34).

Abstract: A dielectrically isolated photodiode having an increased p-n junction size with improved photo-carrier collection efficiency. The photodiode comprises a first layer of semiconductor material formed on the bottom and the walls of an isolation region; a second layer of semiconductor material formed on the first layer. The second layer forming a first p-n junction with the first layer and having opposite conductivity type compared to that of the first layer. The photodiode also comprises a third layer of semiconductor material formed on the second layer and electrically coupled to the first layer. The third layer having the same conductivity type as the first layer and forming a second p-n junction with the second layer. During operation, the first p-n junction functions to collect photo-generated carriers that extend to the bottom and walls of the isolation region, thereby increasing the active collecting p-n junction area per isolation region area to improve efficiency of the photodiode.

Abstract: A radial type of high voltage solid-state switch is essentially a gated diode switch (GDS) with portions of the anode, cathode, shield, and gate regions being arc portions of concentric circles which have different radii. The arc length and radius of the arc portions of the anode are less than the corresponding parameters of the shield and cathode. This structure, which is denoted as a radial gated diode switch, RGDS, has lower on resistance than a standard GDS of the same area and distance between anode and shield regions.