Abstract: A cooling system for an electronic component on a component carrier is provided. The system includes a frame, a spray manifold, and a sealing member. The frame has an opening and is connectable to the component carrier so that an annular area is defined between the opening and the electronic component. The spray manifold is sealed over the opening to define a spray area over a back surface of the electronic component. The spray manifold sprays a cooling fluid on the back surface. The sealing member seals the annular region so that input/output connectors on the component carrier are isolated from the cooling fluid.

Abstract: Methods of forming and assemblies having hybrid interconnection grid arrays composed of a homogenous mixture of Pb-free solder joints and Pb-containing solder paste on corresponding sites of a printed board. The aligned Pb-free solder joints and Pb-containing solders are heated to a temperature above a melting point of the Pb-free solder joint for a sufficient time to allow complete melting of both the Pb-free solder joints and Pb-containing solder paste and the homogenous mixing thereof during assembly. These molten materials mix together such that the Pb from the Pb-containing solder disperses throughout substantially the entire Pb-free solder joint for complete homogenization of the molten materials to form the homogenous hybrid interconnect structures of the invention.

Abstract: A method for assembling, and the resultant electronic module, includes attaching a chip to a substrate using a first solder interconnection array, and attaching a board to the substrate using a second solder interconnection array, which may be a single-melt or a dual-melt solder array. The second solder interconnection array resides entirely within a space defined between the board and substrate. A creep resistant structure is provided within this space for maintaining the defined space and optimizing integrity of the second solder interconnection array. The creep resistant structure may include an underfill material, balls, brackets, frames, collars or combinations thereof. Wherein the creep resistant structure is an underfill material, it is crucial that the substrate be attached to the board before either entirely encapsulating the second interconnection array with underfill material, or partially encapsulating the second solder interconnection array at discrete locations with underfill material.

Abstract: Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.

Abstract: Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.

Abstract: A multilayer ceramic substrate in which an outer metal pad is anchored to the substrate by a single metal-filled via in the first ceramic layer adjacent to the metal pad. In turn, this single metal-filled via is anchored to the substrate by a larger, single metal-filled via in the next ceramic layer adjacent to the first ceramic layer. Preferably, the metal-filled vias and metal pad are 100 volume percent metal.

Abstract: An electronic package having a solder interconnect liquidus temperature hierarchy to limit the extent of the melting of the C4 solder interconnect during subsequent second level join/assembly and rework operations. The solder hierarchy employs the use of off-eutectic solder alloys of Sn/Ag and Sn/Cu with a higher liquidus temperature for the C4 first level solder interconnections, and a lower liquidus temperature alloy for the second level interconnections. When the second level chip carrier to PCB join/assembly operations occur, the chip to chip carrier C4 interconnections do not melt completely. They continue to have a certain fraction of solids, and a lower fraction of liquids, than a fully molten alloy. This provides reduced expansion of the solder join and consequently lower stresses on the C4 interconnect.

Abstract: Disclosed is an apparatus for separating interconnects between, for example, a card and a substrate. The apparatus includes one or more rotationally biased (e.g., spring-loaded, etc.) partial-circle structures (e.g., blades, squeegee, plow, etc.) and one or more temperature-sensitive releases connected to the partial-circle structures. The partial-circle structures are positioned to rotate and separate the interconnects when released by the temperature-sensitive releases. The invention can also include solder reservoirs positioned to receive solder from the interconnects separated by the partial-circle structures.

Abstract: An inventive method for forming a thin film comprises the steps of preparing a sputter-target of a material which is fully oxidized and crystallized to a perovskite structure, sputter-depositing a thin film on top of a sample with the target in an inert gas atmosphere, and annealing the thin film in non-oxygen ambient. With the use of such a target, it is possible to reduce the negative ion effect during the sputter deposition and to eliminate the presence of oxygen during the annealing process.