Patents by Inventor Mukta Ghate Farooq
Mukta Ghate Farooq has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210143022Abstract: A method of forming a planarized integration structure is provided. The method includes forming at least two conductive pillars on a packaging substrate, wherein the packaging substrate has a positive or convex meniscus shape. The method further includes placing a bridging die on the packaging substrate between an adjacent pair of the at least two conductive pillars, wherein the bridging die includes one or more conductive interconnects. The method further includes forming a cover layer on the substrate over the at least two conductive pillars and the bridging die, and planarizing the conductive pillars and the one or more conductive interconnects.Type: ApplicationFiled: November 8, 2019Publication date: May 13, 2021Inventors: Mukta Ghate Farooq, James Kelly
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Publication number: 20210091032Abstract: Package structures and methods are provided for constructing multi-chip package structures using semiconductor wafer-level-fan-out techniques in conjunction with back-end-of-line fabrication methods to integrate different size chips (e.g., different thicknesses) into a planar package structure. The packaging techniques take into account intra-chip thickness variations and inter-chip thickness differences, and utilize standard back-end-of-line fabrication methods and materials to account for such thickness variations and differences. In addition, the back-end-of-line techniques allow for the formation of multiple layers of wiring and inter-layer vias which provide high density chip-to-chip interconnect wiring for high-bandwidth I/O communication between the package chips, as well as redistribution layers to route power/ground connections between active-side connections of the semiconductor chips to an area array of solder bump interconnects on a bottom side of the multi-chip package structure.Type: ApplicationFiled: September 19, 2019Publication date: March 25, 2021Inventors: Ravi K. Bonam, Mukta Ghate Farooq, Dinesh Gupta, James J. Kelly
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Patent number: 10943883Abstract: Package structures and methods are provided for constructing multi-chip package structures using semiconductor wafer-level-fan-out techniques in conjunction with back-end-of-line fabrication methods to integrate different size chips (e.g., different thicknesses) into a planar package structure. The packaging techniques take into account intra-chip thickness variations and inter-chip thickness differences, and utilize standard back-end-of-line fabrication methods and materials to account for such thickness variations and differences. In addition, the back-end-of-line techniques allow for the formation of multiple layers of wiring and inter-layer vias which provide high density chip-to-chip interconnect wiring for high-bandwidth I/O communication between the package chips, as well as redistribution layers to route power/ground connections between active-side connections of the semiconductor chips to an area array of solder bump interconnects on a bottom side of the multi-chip package structure.Type: GrantFiled: September 19, 2019Date of Patent: March 9, 2021Assignee: International Business Machines CorporationInventors: Ravi K. Bonam, Mukta Ghate Farooq, Dinesh Gupta, James J. Kelly
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Publication number: 20210005573Abstract: A semiconductor wafer includes a first substrate and a first etch stop layer formed on the first substrate. The etch stop layer has an opening. The semiconductor wafer further includes a second substrate and a second etch stop layer formed on the second substrate. The first substrate is bonded on top of the second substrate such that the first etch stop layer is positioned between the first substrate and the second substrate. A trench is formed in the opening.Type: ApplicationFiled: July 1, 2019Publication date: January 7, 2021Inventors: Ravi K. Bonam, Mukta Ghate Farooq, Dinesh Gupta, James Kelly, Kamal K. Sikka, JOSHUA M. RUBIN
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Patent number: 10199315Abstract: An IC structure and related method are provided. The IC structure includes: a semiconductor substrate and a TSV disposed within the semiconductor substrate. A first interconnect layer includes a plurality of V0 vias disposed on the TSV, where the plurality of V0 vias are positioned laterally within an upper surface area of the TSV. At least one second interconnect layer disposed over the first interconnect layer includes a plurality of vias laterally positioned outside of a keep out zone positioned over the TSV. The method includes forming a first interconnect layer including a plurality of V0 vias disposed on a TSV, the V0 vias positioned laterally within an upper surface area of the TSV, and forming at least one second interconnect layer disposed over the first interconnect layer and including a plurality of vias laterally positioned outside of a keep out zone positioned over the TSV.Type: GrantFiled: August 29, 2016Date of Patent: February 5, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Mukta Ghate Farooq, John Matthew Safran
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Publication number: 20180061749Abstract: An IC structure and related method are provided. The IC structure includes: a semiconductor substrate and a TSV disposed within the semiconductor substrate. A first interconnect layer includes a plurality of V0 vias disposed on the TSV, where the plurality of V0 vias are positioned laterally within an upper surface area of the TSV. At least one second interconnect layer disposed over the first interconnect layer includes a plurality of vias laterally positioned outside of a keep out zone positioned over the TSV. The method includes forming a first interconnect layer including a plurality of V0 vias disposed on a TSV, the V0 vias positioned laterally within an upper surface area of the TSV, and forming at least one second interconnect layer disposed over the first interconnect layer and including a plurality of vias laterally positioned outside of a keep out zone positioned over the TSV.Type: ApplicationFiled: August 29, 2016Publication date: March 1, 2018Inventors: Mukta Ghate Farooq, John Matthew Safran
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Patent number: 8367543Abstract: A system and method comprises depositing a dielectric layer on a substrate and depositing a metal layer on the dielectric layer. The system and method further includes depositing a high temperature diffusion barrier metal cap on the metal layer. The system and method further includes depositing a second dielectric layer on the high temperature diffusion barrier metal cap and the first dielectric layer, and etching a via into the second dielectric layer, such that the high temperature diffusion barrier metal cap is exposed. The system and method further includes depositing an under bump metallurgy in the via, and forming a C4 ball on the under bump metallurgy layer.Type: GrantFiled: March 21, 2006Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Mukta Ghate Farooq, Jasvir Singh Jaspal, William Francis Landers, Thomas E. Lombardi, Hai Pham Longworth, H. Bernhard Pogge, Roger A. Quon
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Patent number: 8129842Abstract: The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping material. The barrier can be either partially embedded in the cap layer or completely embedded in the capping layer.Type: GrantFiled: January 19, 2009Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Mukta Ghate Farooq, Keith Kwong Hon Wong, Haining Yang
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Patent number: 7714452Abstract: An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically conductive member. The fourth electrically conductive pad comprises a height that is different than a height of the first electrically conductive member. The electrically conductive member is electrically and mechanically connected to the fourth electrically conductive pad. A first solder ball connects the first electrically conductive pad to the third electrically conductive pad. The first solder ball comprises a first diameter. A second solder ball connects the second electrically conductive pad to the first electrically conductive member. The second solder ball comprises a second diameter. The first diameter is greater than said second diameter.Type: GrantFiled: August 30, 2007Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Mukta Ghate Farooq, Louis Lu-Chen Hsu, William Francis Landers, Donna S. Zupanski-Nielson, Carl John Radens, Chih-Chao Yang
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Publication number: 20090200669Abstract: The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping material. The barrier can be either partially embedded in the cap layer or completely embedded in the capping layer.Type: ApplicationFiled: January 19, 2009Publication date: August 13, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: CHIH-CHAO YANG, Mukta Ghate Farooq, Keith Kwong Hon Wong, Haining Yang
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Patent number: 7531384Abstract: The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping material. The barrier can be either partially embedded in the cap layer or completely embedded in the capping layer.Type: GrantFiled: October 11, 2006Date of Patent: May 12, 2009Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Mukta Ghate Farooq, Keith Kwong Hon Wong, Haining Yang
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Patent number: 7473580Abstract: An improved method for performing an improved Temporary Chip Attach utilizing an Injection Molded Solder (IMS) process to allow efficient testing of die for creating a Known Good Die Bank. The IMS is applied to the testing substrate to form a column on the substrate. The die to be tested can then be attached to the IMS column with C4 solder. A slight reflow is then applied to the die, allowing some of the C4 to melt, and form an electrical connection with the corresponding IMS column. After testing, the die can be removed along with the C4 from the IMS column or permanently attached the substrate by performing a full reflow of the C4.Type: GrantFiled: May 18, 2006Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Mukta Ghate Farooq, Thomas J Fleischman
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Publication number: 20080224328Abstract: An improved method for performing an improved Temporary Chip Attach utilizing an Injection Molded Solder (IMS) process to allow efficient testing of die for creating a Known Good Die Bank. The IMS is applied to the testing substrate to form a column on the substrate. The die to be tested can then be attached to the IMS column with C4 solder. A slight reflow is then applied to the die, allowing some of the C4 to melt, and form an electrical connection with the corresponding IMS column. After testing, the die can be removed along with the C4 from the IMS column or permanently attached the substrate by performing a full reflow of the C4.Type: ApplicationFiled: May 20, 2008Publication date: September 18, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta Ghate Farooq, Thomas J. Fleischman
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Publication number: 20080160752Abstract: A damascene method of forming a C4 element includes forming a last level metal layer on a substrate, forming a TV ILD layer on the last level metal layer, forming a lithographically patterned UBM adhesion layer including one of Ti, TiW, Cr and Cu, forming a mandrel layer over the UBM adhesion layer, lithographically patterning the mandrel layer to form an aperture, depositing a solder layer by one of sputtering, evaporation, physical vapor deposition, solder wave or injection molding in the aperture, planarizing the solder layer by CMP, removing the mandrel layer, reflowing the solder to ball the solder to form a ball interconnect, and joining a second substrate with an I/O pad to the ball interconnect.Type: ApplicationFiled: January 3, 2007Publication date: July 3, 2008Applicant: International Business Machines CorporationInventors: Lawrence Clevenger, Timothy J. Dalton, Mukta Ghate Farooq, William Francis Landers, Carl Radens, Chih-Chao Yang
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Publication number: 20080088026Abstract: The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping material. The barrier can be either partially embedded in the cap layer or completely embedded in the capping layer.Type: ApplicationFiled: October 11, 2006Publication date: April 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Chao Yang, Mukta Ghate Farooq, Keith Kwong Hon Wong, Haining Yang
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Publication number: 20070269928Abstract: An improved method for performing an improved Temporary Chip Attach utilizing an Injection Molded Solder (IMS) process to allow efficient testing of die for creating a Known Good Die Bank. The IMS is applied to the testing substrate to form a column on the substrate. The die to be tested can then be attached to the IMS column with C4 solder. A slight reflow is then applied to the die, allowing some of the C4 to melt, and form an electrical connection with the corresponding IMS column. After testing, the die can be removed along with the C4 from the IMS column or permanently attached the substrate by performing a full reflow of the C4.Type: ApplicationFiled: May 18, 2006Publication date: November 22, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta Ghate Farooq, Thomas J. Fleischman
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Patent number: 6943108Abstract: An interposer, located between an integrated circuit having power, ground and signal connections and a ceramic substrate having power, ground and signal connections, that includes an oxide layer formed on a polished surface of a silicon substrate, a thin film dielectric capacitor formed on the oxide layer, a plurality of metallized that electrically connect to either of the electrodes of the thin film dielectric capacitor, and vias than conduct power, ground and signals between a the ceramic substrate and the integrated circuit. The interposer connects the metallized vias to the integrated circuit by solder connections and also connects the vias conducting power, ground and signals from the ceramic substrate to the interposer by solder connections.Type: GrantFiled: July 8, 2004Date of Patent: September 13, 2005Assignee: International Business Machines CorporationInventors: Mukta Ghate Farooq, John U. Knickerbocker, Srinivasa Reddy, Robert Anthony Rita
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Publication number: 20040245556Abstract: An interposer, located between an integrated circuit having power, ground and signal connections and a ceramic substrate having power, ground and signal connections, that includes an oxide layer formed on a polished surface of a silicon substrate, a thin film dielectric capacitor formed on the oxide layer, a plurality of metallized that electrically connect to either of the electrodes of the thin film dielectric capacitor, and vias than conduct power, ground and signals between a the ceramic substrate and the integrated circuit. The interposer connects the metallized vias to the integrated circuit by solder connections and also connects the vias conducting power, ground and signals from the ceramic substrate to the interposer by solder connections.Type: ApplicationFiled: July 8, 2004Publication date: December 9, 2004Applicant: International Business Machines CorporationInventors: Mukta Ghate Farooq, John U. Knickerbocker, Srinivasa Reddy, Robert Anthony Rita
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Patent number: 6791133Abstract: An interposer, located between an integrated circuit having power, ground and signal connections and a ceramic substrate having power, ground and signal connections, that includes an oxide layer formed on a polished surface of a silicon substrate, a thin film dielectric capacitor formed on the oxide layer, a plurality of metallized that electrically connect to either of the electrodes of the thin film dielectric capacitor, and vias than conduct power, ground and signals between a the ceramic substrate and the integrated circuit. The interposer connects the metallized vias to the integrated circuit by solder connections and also connects the vias conducting power, ground and signals from the ceramic substrate to the interposer by solder connections.Type: GrantFiled: July 19, 2002Date of Patent: September 14, 2004Assignee: International Business Machines CorporationInventors: Mukta Ghate Farooq, John U. Knickerbocker, Srinivasa Reddy, Robert Anthony Rita
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Publication number: 20040014313Abstract: An interposer, located between an integrated circuit having power, ground and signal connections and a ceramic substrate having power, ground and signal connections, that includes an oxide layer formed on a polished surface of a silicon substrate, a thin film dielectric capacitor formed on the oxide layer, a plurality of metallized that electrically connect to either of the electrodes of the thin film dielectric capacitor, and vias than conduct power, ground and signals between a the ceramic substrate and the integrated circuit. The interposer connects the metallized vias to the integrated circuit by solder connections and also connects the vias conducting power, ground and signals from the ceramic substrate to the interposer by solder connections.Type: ApplicationFiled: July 19, 2002Publication date: January 22, 2004Applicant: International Business Machines CorporationInventors: Mukta Ghate Farooq, John U. Knickerbocker, Srinivasa Reddy, Robert Anthony Rita