Abstract: A computerized virtual entity pathway visualization method and system provide a virtual entity packet pathway display indicating a packet pathway along which a data packet would travel from between virtual entities (e.g., virtual machines) in a computer system. One implementation includes modeling of a computer system having physical and virtual entities, identifying a packet pathway from a source virtual entity in the computer system to a destination virtual entity in the computer system, and rendering on a computer display screen a packet pathway and an arrangement of plural active icons corresponding to physical and virtual entities included in the packet pathway from the source virtual entity to the destination virtual entity.

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes power rails that provide power to the transistors. The power rails extend in a second direction orthogonal to the first direction. The device further includes M1 layer interconnects extending between the power rails. At least one of the M1 layer interconnects is coupled to at least one of the transistors. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only.

Abstract: A computerized datacenter entity information method includes obtaining datacenter entity information at an initial time, compressing and storing the datacenter entity information as a datacenter entity frame of reference, obtaining datacenter entity information changes, and compressing and storing the datacenter entity information changes with respect to the datacenter entity frame of reference. In another implementation, the computerized datacenter entity information method includes obtaining datacenter entity information at an initial time, compressing and storing the datacenter entity information as a datacenter entity frame of reference, obtaining datacenter entity information changes, and compressing and storing the datacenter entity information changes with respect to the datacenter entity frame of reference.

Abstract: A datacenter management system uses data collection proxies to collect performance data and configuration data for different physical and virtual entities in the datacenter. A schema is used to represent the different entities, entity relationships, and entity properties in the datacenter. A search engine identifies the intent of a natural language based search query based on the schema and a datacenter dictionary. The search engine then searches the data based on the search query intent. A dictionary manager converts both periodic and aperiodic data into a time series. This allows the search engine to operate as a time machine identifying both performance data and configuration data for any selectable time period.

Abstract: A standard cell IC includes pMOS transistors in a pMOS region of a MOS device. The pMOS region extends between a first cell edge and a second cell edge opposite the first cell edge. The standard cell IC further includes nMOS transistors in an nMOS region of the MOS device. The nMOS region extends between the first cell edge and the second cell edge. The standard cell IC further includes at least one single diffusion break located in an interior region between the first cell edge and the second cell edge that extends across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions. The standard cell IC includes a first double diffusion break portion at the first cell edge. The standard cell IC further includes a second double diffusion break portion at the second cell edge.

Abstract: A standard cell IC includes pMOS transistors in a pMOS region of a MOS device. The pMOS region extends between a first cell edge and a second cell edge opposite the first cell edge. The standard cell IC further includes nMOS transistors in an nMOS region of the MOS device. The nMOS region extends between the first cell edge and the second cell edge. The standard cell IC further includes at least one single diffusion break located in an interior region between the first cell edge and the second cell edge that extends across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions. The standard cell IC includes a first double diffusion break portion at the first cell edge. The standard cell IC further includes a second double diffusion break portion at the second cell edge.

Abstract: A datacenter management system uses data collection proxies to collect performance data and configuration data for different physical and virtual entities in the datacenter. A schema is used to represent the different entities, entity relationships, and entity properties in the datacenter. A search engine identifies the intent of a natural language based search query based on the schema and a datacenter dictionary. The search engine then searches the data based on the search query intent. A dictionary manager converts both periodic and aperiodic data into a time series. This allows the search engine to operate as a time machine identifying both performance data and configuration data for any selectable time period.

Abstract: Tire comprising a crown reinforcement formed of at least two working crown layers of reinforcing elements, crossed from one layer to the other making with the circumferential direction angles comprised between 10° and 45°. A first layer S of polymer compound is in contact with at least one working crown layer and in contact with the carcass reinforcement, the said first layer S of polymer compound extending axially as far as at least the axial end of the tread and the complex dynamic shear modulus G*, measured at 10% and 60° C. on the return cycle, of the first layer S of polymer compound is greater than 1.35 MPa.

Abstract: Tire comprising a crown reinforcement formed of at least two working crown layers of reinforcing elements, crossed from one layer to the other making with the circumferential direction angles comprised between 10° and 45°. A first layer S of polymer compound is in contact with at least one working crown layer and in contact with the carcass reinforcement, the first layer S of polymer compound extending axially as far as at least the axial end of the tread, the first layer S of compound polymer compound is made up of a filled elastomer blend having a macro dispersion coefficient Z greater than or equal to 65 and a maximum tan(?) value, denoted tan(?)max, less than 0.100 and its complex dynamic shear modulus G*, measured at 10% and 60° C. on the return cycle is greater than 1.35 MPa.

Abstract: A MOS device includes first, second, third, and fourth interconnects. The first interconnect extends on a first track in a first direction. The first interconnect is configured in a metal layer. The second interconnect extends on the first track in the first direction. The second interconnect is configured in the metal layer. The third interconnect extends on a second track in the first direction. The third interconnect is configured in the metal layer. The second track is parallel to the first track. The third interconnect is coupled to the second interconnect. The second and third interconnects are configured to provide a first signal. The fourth interconnect extends on the second track in the first direction. The fourth interconnect is configured in the metal layer. The fourth interconnect is coupled to the first interconnect. The first and fourth interconnects are configured to provide a second signal different than the first signal.

Abstract: A MOS device includes a first MOS transistor having a first MOS transistor source, a first MOS transistor drain, and a first MOS transistor gate. The MOS device also includes a second MOS transistor having a second MOS transistor source, a second MOS transistor drain, and a second MOS transistor gate. The second MOS transistor source and the first MOS transistor source are coupled to a first voltage source. The MOS device includes a third MOS transistor having a third MOS transistor gate, the third MOS transistor gate between the first MOS transistor source and the third MOS transistor source, the third MOS transistor further having a third MOS transistor source and a third MOS transistor drain, the third MOS transistor source being coupled to the first MOS transistor source, the third MOS transistor drain being coupled to the second MOS transistor source, the third MOS transistor gate floating.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.

Abstract: A MOS device includes first, second, third, and fourth interconnects. The first interconnect extends on a first track in a first direction. The first interconnect is configured in a metal layer. The second interconnect extends on the first track in the first direction. The second interconnect is configured in the metal layer. The third interconnect extends on a second track in the first direction. The third interconnect is configured in the metal layer. The second track is parallel to the first track. The third interconnect is coupled to the second interconnect. The second and third interconnects are configured to provide a first signal. The fourth interconnect extends on the second track in the first direction. The fourth interconnect is configured in the metal layer. The fourth interconnect is coupled to the first interconnect. The first and fourth interconnects are configured to provide a second signal different than the first signal.

Abstract: The invention relates to an improved double break contact system for use in moulded case circuit breakers. The system comprises shaft means (8), fixed contact means (1 and 2) and moving contact means (3) mounted on shaft means (8), spring means (4) operatively mounted on the shaft means (8), holder means (5) securing said spring means (4) wherein holder means being rotatably mounted on the shaft means in a manner that rotation of the shaft means in operation rotates said holder means. The spring means is adapted to provide force opposing the electromagnetic.

Abstract: A MOS device includes a first interconnect extending in a first direction, the first interconnect being configured in a metal layer. The MOS device further includes a second interconnect extending in the first direction parallel to the first interconnect, the second interconnect being configured in the metal layer. The MOS device further includes a gate interconnect extending in a second direction orthogonal to the first direction, the gate interconnect being situated in a first layer below the metal layer, wherein the gate interconnect is coupled to the first interconnect by a first via. The MOS device further includes a third interconnect extending in the second direction, the third interconnect being coupled to both the first and second interconnects, wherein the third interconnect is coupled to the first interconnect by a second via, and wherein the second via contacts the first via.

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes power rails that provide power to the transistors. The power rails extend in a second direction orthogonal to the first direction. The device further includes M1 layer interconnects extending between the power rails. At least one of the M1 layer interconnects is coupled to at least one of the transistors. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only.

Abstract: In an embodiment, a method in the manufacture of triple-patterning lithography masks, each mask represented by one of three colors, where each cell layout has exactly one polygonal pattern at one-half the different-color spacing from its left boundary, and exactly one polygonal pattern at one-half the different-color spacing from its right boundary. During placement of the cell layouts into a row, the method includes switching assigned colors in a cell layout to ensure that no two polygonal patterns of the same color in the layout are at a distance from each other less than the same-color spacing.

Abstract: An integrated circuit includes a capacitor having first, second and third nodes. The first and second nodes of the first transistor are connected together and the first and second nodes of the second transistor are connected together. The third node of the first transistor is connected to the third node of the second transistor. Each of the third nodes is constructed so that each node comprises a width and a length that is at least ten percent of the width.

Abstract: The invention relates to an improved double break contact system for use in moulded case circuit breakers. The system comprises shaft means (8), fixed contact means (1 and 2) and moving contact means (3) mounted on shaft means (8), spring means (4) operatively mounted on the shaft means (8), holder means (5) securing said spring means (4) wherein holder means being rotatably mounted on the shaft means in a manner that rotation of the shaft means in operation rotates said holder means.

Abstract: An integrated circuit includes a capacitor having first, second and third nodes. The first and second nodes of the first transistor are connected together and the first and second nodes of the second transistor are connected together. The third node of the first transistor is connected to the third node of the second transistor. Each of the third nodes is constructed so that each node comprises a width and a length that is at least ten percent of the width.