Patents by Inventor Mukul Renavikar

Mukul Renavikar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240030086
    Abstract: Embodiments include semiconductor packages and methods of forming such packages. A semiconductor package includes a die on a package substrate, an integrated heat spreader (IHS) on the package substrate and above the die, and a solder thermal interface material (STIM) coupling the die to the IHS. The semiconductor package includes a low-temperature solder (LTS) paste comprising an alloy of tin and bismuth (Bi), and the LTS paste on a bottom surface of the package substrate having a ball grid array. The LTS paste may have a weight percentage of Bi greater than 35% and a melting point less than or equal to a melting point of the STIM, where the STIM includes indium. The weight percentage of Bi may be between approximately 35% to 58%. The semiconductor package may include a solder ball coupling the LTS paste on the package substrate to the LTS paste on a second package substrate.
    Type: Application
    Filed: October 3, 2023
    Publication date: January 25, 2024
    Inventors: Rajasekaran SWAMINATHAN, Mukul RENAVIKAR
  • Patent number: 11817364
    Abstract: Embodiments include semiconductor packages and methods of forming such packages. A semiconductor package includes a die on a package substrate, an integrated heat spreader (IHS) on the package substrate and above the die, and a solder thermal interface material (STIM) coupling the die to the IHS. The semiconductor package includes a low-temperature solder (LTS) paste comprising an alloy of tin and bismuth (Bi), and the LTS paste on a bottom surface of the package substrate having a ball grid array. The LTS paste may have a weight percentage of Bi greater than 35% and a melting point less than or equal to a melting point of the STIM, where the STIM includes indium. The weight percentage of Bi may be between approximately 35% to 58%. The semiconductor package may include a solder ball coupling the LTS paste on the package substrate to the LTS paste on a second package substrate.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: November 14, 2023
    Assignee: Intel Corporation
    Inventors: Rajasekaran Swaminathan, Mukul Renavikar
  • Publication number: 20190393121
    Abstract: Embodiments include semiconductor packages and methods of forming such packages. A semiconductor package includes a die on a package substrate, an integrated heat spreader (IHS) on the package substrate and above the die, and a solder thermal interface material (STIM) coupling the die to the IHS. The semiconductor package includes a low-temperature solder (LTS) paste comprising an alloy of tin and bismuth (Bi), and the LTS paste on a bottom surface of the package substrate having a ball grid array. The LTS paste may have a weight percentage of Bi greater than 35% and a melting point less than or equal to a melting point of the STIM, where the STIM includes indium. The weight percentage of Bi may be between approximately 35% to 58%. The semiconductor package may include a solder ball coupling the LTS paste on the package substrate to the LTS paste on a second package substrate.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventors: Rajasekaran SWAMINATHAN, Mukul RENAVIKAR
  • Publication number: 20190057936
    Abstract: A transmissive composite film is described that may be applied to the backside of a microelectronic device, for example an integrated circuit die or a bridge. A microelectronic die package in one example has a substrate, an integrated circuit die attached and electrically connected to the substrate, the die having a front side with electrical attachments and a backside, and a composite film attached to a backside of the die, the composite film having a polymer base with nano-fillers to protect the backside of the die.
    Type: Application
    Filed: December 18, 2015
    Publication date: February 21, 2019
    Inventors: Mohit GUPTA, Mukul RENAVIKAR
  • Patent number: 8733620
    Abstract: A solder is deposited on a heat sink. The solder is first reflowed at a first temperature that is below about 120° C. The solder is second heat aged at a temperature that causes the first reflowed solder to have an increased second reflow temperature. The heat aging process results in less compressive stress in a die that uses the solder as a thermal interface material. The solder can have a composition that reflows and adheres to the die and the heat sink without the use of organic fluxes.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: May 27, 2014
    Assignee: Intel Corporation
    Inventors: Mukul Renavikar, Susheel G. Jadhav
  • Patent number: 8436470
    Abstract: A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: May 7, 2013
    Assignee: Intel Corporation
    Inventors: Daewoong Suh, Stephen E. Lehman, Mukul Renavikar
  • Patent number: 8409929
    Abstract: In one embodiment, the present invention includes a method for placing a thermal interface material (TIM) between a die including a backside metallic (BSM) layer including copper (Cu) and a heat spreader having a contact surface including Cu, where the TIM is formed of an alloy including indium (In) and tin (Sn), and bonding the TIM to the die and the heat spreader to form at least one quaternary intermetallic compound (IMC) layer. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: April 2, 2013
    Assignee: Intel Corporation
    Inventors: Mukul Renavikar, Daewoong Suh, Carl Deppisch, Abhishek Gupta
  • Publication number: 20110312131
    Abstract: In one embodiment, the present invention includes a method for placing a thermal interface material (TIM) between a die including a backside metallic (BSM) layer including copper (Cu) and a heat spreader having a contact surface including Cu, where the TIM is formed of an alloy including indium (In) and tin (Sn), and bonding the TIM to the die and the heat spreader to form at least one quaternary intermetallic compound (IMC) layer. Other embodiments are described and claimed.
    Type: Application
    Filed: August 30, 2011
    Publication date: December 22, 2011
    Inventors: Mukul Renavikar, Daewoong Suh, Carl Deppisch, Abhishek Gupta
  • Patent number: 8030757
    Abstract: In one embodiment, the present invention includes a method for placing a thermal interface material (TIM) between a die including a backside metallic (BSM) layer including copper (Cu) and a heat spreader having a contact surface including Cu, where the TIM is formed of an alloy including indium (In) and tin (Sn), and bonding the TIM to the die and the heat spreader to form at least one quaternary intermetallic compound (IMC) layer. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: October 4, 2011
    Assignee: Intel Corporation
    Inventors: Mukul Renavikar, Daewoong Suh, Carl Deppisch, Abhishek Gupta
  • Patent number: 8018063
    Abstract: A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: September 13, 2011
    Assignee: Intel Corporation
    Inventors: Daewoong Suh, Stephen E. Lehman, Jr., Mukul Renavikar
  • Publication number: 20110051376
    Abstract: A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni.
    Type: Application
    Filed: November 8, 2010
    Publication date: March 3, 2011
    Applicant: INTEL, INC.
    Inventors: Daewoong Suh, Stephen E. Lehman, JR., Mukul Renavikar
  • Patent number: 7700476
    Abstract: A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Daewoong Suh, Stephen E. Lehman, Jr., Mukul Renavikar
  • Publication number: 20100044848
    Abstract: A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni.
    Type: Application
    Filed: October 30, 2009
    Publication date: February 25, 2010
    Inventors: Daewoong Suh, Stephen E. Lehman, JR., Mukul Renavikar
  • Publication number: 20090001557
    Abstract: In one embodiment, the present invention includes a method for placing a thermal interface material (TIM) between a die including a backside metallic (BSM) layer including copper (Cu) and a heat spreader having a contact surface including Cu, where the TIM is formed of an alloy including indium (In) and tin (Sn), and bonding the TIM to the die and the heat spreader to form at least one quaternary intermetallic compound (IMC) layer. Other embodiments are described and claimed.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventors: Mukul Renavikar, Daewoong Suh, Carl Deppisch, Abhishek Gupta
  • Publication number: 20080115968
    Abstract: A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni.
    Type: Application
    Filed: November 20, 2006
    Publication date: May 22, 2008
    Inventors: Daewoong Suh, Stephen E. Lehman, Mukul Renavikar
  • Publication number: 20070228111
    Abstract: A method of forming a microelectronic package, a microelectronic package formed according to the method, and a system including the microelectronic package. The method comprises: providing a die-substrate combination including: providing a die having die bumping sites thereon each including a layer comprising a stabilizing element; providing a substrate having substrate bumping sites thereon; before heating, placing a solder on at least one of the die bumping sites and the substrate bumping sites, the solder including a first solder element and a second solder element; and placing the die and the substrate in registration with one another to sandwich the solder therebetween. The method further comprises forming a plurality of joint structures including heating the die-substrate combination to reflow the solder.
    Type: Application
    Filed: March 29, 2006
    Publication date: October 4, 2007
    Inventors: Ganesh Vasudevanpillai, Mukul Renavikar, Jessica Weninger
  • Publication number: 20070206356
    Abstract: An integrated heat spreader and die coupled with solder are disclosed herein. The heat spreader may have solder reservoirs. Additionally, the heat spreader and die may be coupled during a reflow process where the gaseous pressure surrounding the integrated heat spreader and the die is varied.
    Type: Application
    Filed: May 10, 2007
    Publication date: September 6, 2007
    Inventors: Thomas Fitzgerald, Mukul Renavikar, Susheel Jadhav
  • Publication number: 20070131737
    Abstract: A solder is deposited on a heat sink. The solder is first reflowed at a first temperature that is below about 120° C. The solder is second heat aged at a temperature that causes the first reflowed solder to have an increased second reflow temperature. The heat aging process results in less compressive stress in a die that uses the solder as a thermal interface material. The solder can have a composition that reflows and adheres to the die and the heat sink without the use of organic fluxes.
    Type: Application
    Filed: December 8, 2005
    Publication date: June 14, 2007
    Inventors: Mukul Renavikar, Susheel Jadhav
  • Publication number: 20070117270
    Abstract: Integrated heat spreader and die coupled with solder in a manner forming an intermetallic compound having a higher liquidus temperature than the liquidus temperature of the solder used to create the intermetallic compound are described herein.
    Type: Application
    Filed: January 22, 2007
    Publication date: May 24, 2007
    Inventors: Mukul Renavikar, Susheel Jadhav
  • Publication number: 20060227510
    Abstract: Integrated heat spreader and die coupled with solder. The heat spreader may have solder reservoirs. Additionally, the heat spreader and die may be coupled during a reflow process where the gaseous pressure surrounding the integrated heat spreader and the die is varied.
    Type: Application
    Filed: April 11, 2005
    Publication date: October 12, 2006
    Inventors: Thomas Fitzgerald, Mukul Renavikar, Susheel Jadhav