Patents by Inventor Mun-Mo Jeong
Mun-Mo Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9287395Abstract: A semiconductor device comprises: a semiconductor substrate including a cell region and a peripheral region; an insulating film formed on the top portion of the semiconductor substrate of the cell region; a bit line contact hole including the etched insulating film to expose the semiconductor substrate; a bit line contact plug buried in the bit line contact plug; and a bit line formed on the top portion of the bit line contact plug to have the same width as that of the bit line contact plug. The thickness of the insulating film around a cell bit line is minimized so as to vertically form a profile of the cell bit line, thereby improving an overlay margin of a storage node contact and an active region.Type: GrantFiled: September 9, 2013Date of Patent: March 15, 2016Assignee: SK HYNIX INC.Inventor: Mun Mo Jeong
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Publication number: 20140008719Abstract: A semiconductor device comprises: a semiconductor substrate including a cell region and a peripheral region; an insulating film formed on the top portion of the semiconductor substrate of the cell region; a bit line contact hole including the etched insulating film to expose the semiconductor substrate; a bit line contact plug buried in the bit line contact plug; and a bit line formed on the top portion of the bit line contact plug to have the same width as that of the bit line contact plug. The thickness of the insulating film around a cell bit line is minimized so as to vertically form a profile of the cell bit line, thereby improving an overlay margin of a storage node contact and an active region.Type: ApplicationFiled: September 9, 2013Publication date: January 9, 2014Applicant: SK HYNIX INC.Inventor: Mun Mo JEONG
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Patent number: 8309449Abstract: A semiconductor and a method for forming the same are disclosed. The method for forming the semiconductor device includes forming a buried gate on a semiconductor substrate including an active region, forming an insulating layer on the semiconductor substrate, selectively removing the insulating layer from at least an upper part of the active region, forming a bit line on an upper part between the buried gates formed on the active region, and forming a storage electrode contact that is formed at both sides of the bit line and has an extended lower part, so that prevents short circuiting between the storage electrode contact and the bit line, and improves contact resistance by enlarging a contact area between the storage electrode contact and the active region, so that unique characteristics of the semiconductor device are improved.Type: GrantFiled: December 30, 2009Date of Patent: November 13, 2012Assignee: Hynix Semiconductor Inc.Inventors: Mun Mo Jeong, Dong Geun Lee
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Publication number: 20120012911Abstract: A semiconductor device comprises: a semiconductor substrate including a cell region and a peripheral region; an insulating film formed on the top portion of the semiconductor substrate of the cell region; a bit line contact hole including the etched insulating film to expose the semiconductor substrate; a bit line contact plug buried in the bit line contact plug; and a bit line formed on the top portion of the bit line contact plug to have the same width as that of the bit line contact plug. The thickness of the insulating film around a cell bit line is minimized so as to vertically form a profile of the cell bit line, thereby improving an overlay margin of a storage node contact and an active region.Type: ApplicationFiled: July 20, 2010Publication date: January 19, 2012Applicant: Hynix Semiconductor Inc.Inventor: Mun Mo JEONG
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Publication number: 20100327346Abstract: A semiconductor and a method for forming the same are disclosed. The method for forming the semiconductor device includes forming a buried gate on a semiconductor substrate including an active region, forming an insulating layer on the semiconductor substrate, selectively removing the insulating layer from at least an upper part of the active region, forming a bit line on an upper part between the buried gates formed on the active region, and forming a storage electrode contact that is formed at both sides of the bit line and has an extended lower part, so that prevents short circuiting between the storage electrode contact and the bit line, and improves contact resistance by enlarging a contact area between the storage electrode contact and the active region, so that unique characteristics of the semiconductor device are improved.Type: ApplicationFiled: December 30, 2009Publication date: December 30, 2010Applicant: Hynix Semiconductor Inc.Inventors: Mun Mo JEONG, Dong Geun Lee
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Patent number: 7566924Abstract: Embodiments of the invention provide a semiconductor device and a fabrication method for a semiconductor device that includes the processes of forming multiple gates on a silicon substrate, forming a gate spacer having a positive slope at the gate spacer edge, depositing a polysilicon layer on the silicon substrate between the gates, etching a portion of the polysilicon layer to form an opening exposing a portion of the silicon substrate, and forming an inter-insulation layer to the exposed portion of the silicon substrate to fill the opening. Using an annealing process applied to a layer in the gate spacer, the etch selectivity can be selectively controlled and consequently, the degree of slope at the gate spacer edge is predetermined.Type: GrantFiled: October 11, 2005Date of Patent: July 28, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Huhn Lee, Mun-Mo Jeong, Wook-je Kim
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Patent number: 7473954Abstract: A semiconductor device with a bitline structure has a stud type capping layer. A method of fabricating the same achieves sufficient process margins and reduces parasitic capacitance. The device may include an insulating film formed on a semiconductor substrate and having a bitline contact and a groove-shaped bitline pattern, a bitline formed on the bitline contact and on a portion of the bitline pattern and that is surrounded by the insulating film, and a bitline capping layer formed on the bitline within the bitline pattern and the insulating film that protrudes from the insulating film. A protruded portion of the bitline capping layer is wider than a width of the bitline.Type: GrantFiled: October 11, 2005Date of Patent: January 6, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Mun-Mo Jeong, Chang-Huhn Lee, Makoto Yoshida
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Patent number: 7217618Abstract: A semiconductor device and method for fabricating same according to an embodiment of the invention includes: preparing a semiconductor substrate having a first contact pad and a second contact pad; forming a first insulating film on the substrate; etching the first insulating film to form a groove-shaped bit line pattern and a contact exposing the first contact pad and the second contact pad, respectively; simultaneously forming a contact plug and a bit line in the contact and the bit line pattern, respectively, the contact plug and the bitline having upper surfaces that are coplanar; and forming a bottom electrode for a capacitor that is connected to the first contact pad.Type: GrantFiled: October 3, 2003Date of Patent: May 15, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Huhn Lee, Mun-Mo Jeong
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Patent number: 7132362Abstract: A semiconductor device having a contact hole capable of maintaining contact resistance of a contact connecting multi-layered interconnections with each other and a method for manufacturing the same are provided. An interconnection layer, a capping layer, and an etching stopper are sequentially formed on a semiconductor substrate. An interlayer insulating layer is deposited over the resulting structure. The etching stopper is formed of a material having a high etching selectivity with respect to the interlayer insulating layer. Then a first contact hole is formed to expose the surface of the etching stopper by etching a predetermined portion of the interlayer insulating layer. Either the etching stopper exposed by the first contact hole or the etching stopper exposed by the first contact hole and part of the capping layer are etched to form a second contact hole.Type: GrantFiled: October 30, 2001Date of Patent: November 7, 2006Assignee: Samsung Electronics Co., Ltd.Inventor: Mun-Mo Jeong
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Publication number: 20060027875Abstract: Embodiments of the invention provide a semiconductor device and a fabrication method for a semiconductor device that includes the processes of forming multiple gates on a silicon substrate, forming a gate spacer having a positive slope at the gate spacer edge, depositing a polysilicon layer on the silicon substrate between the gates, etching a portion of the polysilicon layer to form an opening exposing a portion of the silicon substrate, and forming an inter-insulation layer to the exposed portion of the silicon substrate to fill the opening. Using an annealing process applied to a layer in the gate spacer, the etch selectivity can be selectively controlled and consequently, the degree of slope at the gate spacer edge is predetermined.Type: ApplicationFiled: October 11, 2005Publication date: February 9, 2006Applicant: Samsung Electronics Co., Ltd.Inventors: Chang-Huhn Lee, Mun-Mo Jeong, Wook-je Kim
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Publication number: 20060027852Abstract: A semiconductor device with a bitline structure has a stud type capping layer. A method of fabricating the same achieves sufficient process margins and reduces parasitic capacitance. The device may include an insulating film formed on a semiconductor substrate and having a bitline contact and a groove-shaped bitline pattern, a bitline formed on the bitline contact and on a portion of the bitline pattern and that is surrounded by the insulating film, and a bitline capping layer formed on the bitline within the bitline pattern and the insulating film that protrudes from the insulating film. A protruded portion of the bitline capping layer is wider than a width of the bitline.Type: ApplicationFiled: October 11, 2005Publication date: February 9, 2006Applicant: Samsung Electronics Co., Ltd.Inventors: Mun-Mo Jeong, Chang-Huhn Lee, Makoto Yoshida
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Patent number: 6982199Abstract: A semiconductor device with a bitline structure has a stud type capping layer. A method of fabricating the same achieves sufficient process margins and reduces parasitic capacitance. The device may include an insulating film formed on a semiconductor substrate and having a bitline contact and a groove-shaped bitline pattern, a bitline formed on the bitline contact and on a portion of the bitline pattern and that is surrounded by the insulating film, and a bitline capping layer formed on the bitline within the bitline pattern and the insulating film that protrudes from the insulating film. A protruded portion of the bitline capping layer is wider than the width of the bitline.Type: GrantFiled: August 6, 2003Date of Patent: January 3, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Mun-Mo Jeong, Chang-Huhn Lee, Makoto Yoshida
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Patent number: 6969673Abstract: Embodiments of the invention provide a semiconductor device and a fabrication method for a semiconductor device that includes the processes of forming multiple gates on a silicon substrate, forming a gate spacer having a positive slope at the gate spacer edge, depositing a polysilicon layer on the silicon substrate between the gates, etching a portion of the polysilicon layer to form an opening exposing a portion of the silicon substrate, and forming an inter-insulation layer to the exposed portion of the silicon substrate to fill the opening. Using an annealing process applied to a layer in the gate spacer, the etch selectivity can be selectively controlled and consequently, the degree of slope at the gate spacer edge is predetermined.Type: GrantFiled: July 30, 2003Date of Patent: November 29, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Huhn Lee, Mun-Mo Jeong, Wook-je Kim
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Publication number: 20040077143Abstract: A semiconductor device and method for fabricating same according to an embodiment of the invention includes: preparing a semiconductor substrate having a first contact pad and a second contact pad; forming a first insulating film on the substrate; etching the first insulating film to form a groove-shaped bit line pattern and a contact exposing the first contact pad and the second contact pad, respectively; simultaneously forming a contact plug and a bit line in the contact and the bit line pattern, respectively, the contact plug and the bitline having upper surfaces that are coplanar; and forming a bottom electrode for a capacitor that is connected to the first contact pad.Type: ApplicationFiled: October 3, 2003Publication date: April 22, 2004Inventors: Chang-Huhn Lee, Mun-Mo Jeong
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Publication number: 20040056247Abstract: A semiconductor device with a bitline structure has a stud type capping layer. A method of fabricating the same achieves sufficient process margins and reduces parasitic capacitance.Type: ApplicationFiled: August 6, 2003Publication date: March 25, 2004Inventors: Mun-Mo Jeong, Chang-Huhn Lee, Makoto Yoshida
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Publication number: 20040031994Abstract: Embodiments of the invention provide a semiconductor device and a fabrication method for a semiconductor device that includes the processes of forming multiple gates on a silicon substrate, forming a gate spacer having a positive slope at the gate spacer edge, depositing a polysilicon layer on the silicon substrate between the gates, etching a portion of the polysilicon layer to form an opening exposing a portion of the silicon substrate, and forming an inter-insulation layer to the exposed portion of the silicon substrate to fill the opening. Using an annealing process applied to a layer in the gate spacer, the etch selectivity can be selectively controlled and consequently, the degree of slope at the gate spacer edge is predetermined.Type: ApplicationFiled: July 30, 2003Publication date: February 19, 2004Inventors: Chang-Huhn Lee, Mun-Mo Jeong, Wook-Je Kim
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Publication number: 20020113283Abstract: A semiconductor device having a contact hole capable of maintaining contact resistance of a contact connecting multi-layered interconnections with each other and a method for manufacturing the same are provided. An interconnection layer, a capping layer, and an etching stopper are sequentially formed on a semiconductor substrate. An interlayer insulating layer is deposited over the resulting structure. The etching stopper is formed of a material having a high etching selectivity with respect to the interlayer insulating layer. Then a first contact hole is formed to expose the surface of the etching stopper by etching a predetermined portion of the interlayer insulating layer. Either the etching stopper exposed by the first contact hole or the etching stopper exposed by the first contact hole and part of the capping layer are etched to form a second contact hole.Type: ApplicationFiled: October 30, 2001Publication date: August 22, 2002Applicant: Samsung Electronics Co., LtdInventor: Mun-Mo Jeong
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Patent number: 5795802Abstract: A method for manufacturing a semiconductor device, the method includes the steps of forming an n-type well and a p-type well under a surface of a semiconductor substrate, forming a pad oxide layer having a first thickness on the p-type well and a second thickness on the n-type well, the first thickness being greater than the second thickness, and forming a field oxide layer between the n-type well and the p-type well, the field oxide layer having less bird's beak on the n-type well than on the p-type well.Type: GrantFiled: September 3, 1997Date of Patent: August 18, 1998Assignee: LG Semicon Co., Ltd.Inventors: Sang-Gi Ko, Mun-Mo Jeong
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Patent number: 5780334Abstract: A method of fabricating a capacitor of a semiconductor memory device includes the steps of: forming an interlevel insulating layer on a semiconductor substrate on which the capacitor will be formed, selectively etching a portion of the interlevel insulating layer placed on a capacitor forming portion to form a capacitor node hole, and forming a first temporary layer on the interlevel insulating layer, including a portion of the interlevel insulating layer in which the capacitor node hole is formed; forming a contact hole beneath the capacitor node hole in a capacitor contact portion; forming a conductive layer on the first temporary layer to bury the contact hole and the capacitor node hole, and then forming a second temporary layer on the conductive layer; etching back the second temporary layer through anisotropic etching process to expose the conductive layer, and to simultaneously form a temporary pillar layer inside the capacitor node hole, the temporary pillar layer being substantially surrounded by theType: GrantFiled: October 11, 1996Date of Patent: July 14, 1998Assignee: LG Semicon Co., Ltd.Inventors: Jun-Hee Lim, Mun-Mo Jeong