Patents by Inventor Muneharu Tokunaga
Muneharu Tokunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10819217Abstract: A power conversion device includes: power conversion circuitry including a plurality of submodules connected in series to each other; a protection device generating a protection command for protecting each submodule; and one or more relay devices outputting the protection command to each submodule. The relay device includes: a first communication circuit for communicating with the protection device; and a second communication circuit for communicating with the power conversion circuitry. The first communication circuit transmits the stop command to the second communication circuit through a first communication channel, and transmits different information different from the stop command to the second communication circuit through a second communication channel. The communication speed of communication through the first communication channel is higher than that of communication through the second communication channel.Type: GrantFiled: March 3, 2017Date of Patent: October 27, 2020Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yasunori Ido, Muneharu Tokunaga, Hideaki Ohashi
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Publication number: 20200259411Abstract: A power conversion device includes: power conversion circuitry including a plurality of submodules connected in series to each other; a protection device generating a protection command for protecting each submodule; and one or more relay devices outputting the protection command to each submodule. The relay device includes: a first communication circuit for communicating with the protection device; and a second communication circuit for communicating with the power conversion circuitry. The first communication circuit transmits the stop command to the second communication circuit through a first communication channel, and transmits different information different from the stop command to the second communication circuit through a second communication channel. The communication speed of communication through the first communication channel is higher than that of communication through the second communication channel.Type: ApplicationFiled: March 3, 2017Publication date: August 13, 2020Applicant: Mitsubishi Electric CorporationInventors: Yasunori IDO, Muneharu TOKUNAGA, Hideaki OHASHI
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Publication number: 20160111388Abstract: A technique capable of improving reliability of a semiconductor device is provided. In the present invention, as a wiring board on which a semiconductor chip is mounted, a build-up wiring board is not used but a through wiring board THWB is used. In this manner, in the present invention, the through wiring board formed of only a core layer is used, so that it is not required to consider a difference in thermal expansion coefficient between a build-up layer and the core layer, and besides, it is not required either to consider the electrical disconnection of a fine via formed in the build-up layer because the build-up layer does not exist. As a result, according to the present invention, the reliability of the semiconductor device can be improved while a cost is reduced.Type: ApplicationFiled: December 30, 2015Publication date: April 21, 2016Inventors: Shinji Baba, Masaki Watanabe, Muneharu Tokunaga, Kazuyuki Nakagawa
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Patent number: 9293405Abstract: A technique capable of improving reliability of a semiconductor device is provided. In the present invention, as a wiring board on which a semiconductor chip is mounted, a build-up wiring board is not used but a through wiring board THWB is used. In this manner, in the present invention, the through wiring board formed of only a core layer is used, so that it is not required to consider a difference in thermal expansion coefficient between a build-up layer and the core layer, and besides, it is not required either to consider the electrical disconnection of a fine via formed in the build-up layer because the build-up layer does not exist. As a result, according to the present invention, the reliability of the semiconductor device can be improved while a cost is reduced.Type: GrantFiled: March 22, 2011Date of Patent: March 22, 2016Assignee: Renesas Electronics CorporationInventors: Shinji Baba, Masaki Watanabe, Muneharu Tokunaga, Kazuyuki Nakagawa
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Patent number: 9171814Abstract: To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.Type: GrantFiled: March 11, 2015Date of Patent: October 27, 2015Assignee: Renesas Electronics CorporationInventors: Masaki Watanabe, Shinji Baba, Muneharu Tokunaga, Toshihiro Iwasaki
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Publication number: 20150187720Abstract: To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.Type: ApplicationFiled: March 11, 2015Publication date: July 2, 2015Inventors: Masaki Watanabe, Shinji Baba, Muneharu Tokunaga, Toshihiro Iwasaki
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Patent number: 8994175Abstract: To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.Type: GrantFiled: December 24, 2013Date of Patent: March 31, 2015Assignee: Renesas Electronics CorporationInventors: Masaki Watanabe, Shinji Baba, Muneharu Tokunaga, Toshihiro Iwasaki
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Publication number: 20140284789Abstract: To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.Type: ApplicationFiled: December 24, 2013Publication date: September 25, 2014Applicant: Renesas Electronics CorporationInventors: Masaki Watanabe, Shinji Baba, Muneharu Tokunaga, Toshihiro Iwasaki
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Publication number: 20140008798Abstract: A technique capable of improving reliability of a semiconductor device is provided. In the present invention, as a wiring board on which a semiconductor chip is mounted, a build-up wiring board is not used but a through wiring board THWB is used. In this manner, in the present invention, the through wiring board formed of only a core layer is used, so that it is not required to consider a difference in thermal expansion coefficient between a build-up layer and the core layer, and besides, it is not required either to consider the electrical disconnection of a fine via formed in the build-up layer because the build-up layer does not exist. As a result, according to the present invention, the reliability of the semiconductor device can be improved while a cost is reduced.Type: ApplicationFiled: March 22, 2011Publication date: January 9, 2014Inventors: Shinji Baba, Masaki Watanabe, Muneharu Tokunaga, Kazuyuki Nakagawa
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Patent number: 6777798Abstract: A stacked semiconductor device structure comprising: a plurality of semiconductor modules each of which includes a substrate and at least one semiconductor device mounted on the substrate; a stacking device for stacking the semiconductor modules on one another; and a surface mount device for surface mounting on a further substrate for a system appliance the semiconductor modules stacked on one another by the stacking device.Type: GrantFiled: March 4, 2003Date of Patent: August 17, 2004Assignee: Renesas Technology Corp.Inventors: Takakazu Fukumoto, Muneharu Tokunaga, Tetsuya Matsuura
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Publication number: 20030127729Abstract: A stacked semiconductor device structure comprising: a plurality of semiconductor modules each of which includes a substrate and at least one semiconductor device mounted on the substrate; a stacking device for stacking the semiconductor modules on one another; and a surface mount device for surface mounting on a further substrate for a system appliance the semiconductor modules stacked on one another by the stacking device.Type: ApplicationFiled: March 4, 2003Publication date: July 10, 2003Inventors: Takakazu Fukumoto, Muneharu Tokunaga, Tetsuya Matsuura
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Publication number: 20030043650Abstract: A multilayered memory device with a plurality of BGA packages laminated, which includes a first BGA package and a second BGA package each having ball bumps, a first multilayer board with a wiring pattern connected to the ball bumps on the first BGA package, a second multilayer board with a wiring pattern connected to the ball bumps on the second BGA package, a connecting board provided between the laminated first multilayer board and second multilayer board to connect the wiring pattern included in each of the multilayer boards, and ball bumps provided on the second multilayer board on the side opposite to the side on which said second BGA package is mounted, and connected to the wiring pattern included in the second multilayer board.Type: ApplicationFiled: July 31, 2002Publication date: March 6, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Nobuhiro Kato, Muneharu Tokunaga
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Publication number: 20020105068Abstract: A stacked semiconductor device structure comprising: a plurality of semiconductor modules each of which includes a substrate and at least one semiconductor device mounted on the substrate; a stacking device for stacking the semiconductor modules on one another; and a surface mount device for surface mounting on a further substrate for a system appliance the semiconductor modules stacked on one another by the stacking device.Type: ApplicationFiled: September 7, 2001Publication date: August 8, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Takakazu Fukumoto, Muneharu Tokunaga, Tetsuya Matsuura
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Patent number: D458234Type: GrantFiled: July 12, 2001Date of Patent: June 4, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takakazu Fukumoto, Muneharu Tokunaga, Tetsuya Matsuura
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Patent number: D459316Type: GrantFiled: July 12, 2001Date of Patent: June 25, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takakazu Fukumoto, Muneharu Tokunaga, Tetsuya Matsuura
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Patent number: D459317Type: GrantFiled: July 12, 2001Date of Patent: June 25, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takakazu Fukumoto, Muneharu Tokunaga, Tetsuya Matsuura
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Patent number: D460744Type: GrantFiled: July 10, 2001Date of Patent: July 23, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takakazu Fukumoto, Muneharu Tokunaga, Tetsuya Matsuura
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Patent number: D460951Type: GrantFiled: July 12, 2001Date of Patent: July 30, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takakazu Fukumoto, Muneharu Tokunaga, Tetsuya Matsuura
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Patent number: D461171Type: GrantFiled: July 11, 2001Date of Patent: August 6, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takakazu Fukumoto, Muneharu Tokunaga, Tetsuya Matsuura
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Patent number: D465773Type: GrantFiled: December 4, 2001Date of Patent: November 19, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takakazu Fukumoto, Muneharu Tokunaga, Tetsuya Matsuura