Abstract: A print control device includes a controller that causes a roll printing machine to print a color adjustment chart. The controller, upon reception of a first print instruction to print a first color adjustment chart, temporarily stores the received first color adjustment chart and suspends printing.

Abstract: A print control system that outputs a video signal to a printer, includes: a plurality of print controllers including a first print controller and a second print controller. The first print controller is connected to a printer and includes an administrator that acquires a print job comprising image information, divides the image information of the acquired print job, and distributes the divided image information to the first print controller and the second print controller; and a first RIP processor that generates image data by rasterizing the image information distributed to the first print controller. The second print controller includes a second RIP processor that generates the image data by rasterizing the image information distributed to the second print controller.

Abstract: An image forming apparatus includes a hardware processor including CPUs each including cores, a process being executed by the CPUs, wherein the hardware processor managing the cores causes a first process or a second process to be executed, when the first process is executed, while electric power is uniformly supplied to the cores, allocates a pre-process in which sequential processing is performed to a part of the cores and a post-process in which parallel processing is performed to another part of cores, and when the second process is executed, for a part of the CPUs, allocates the pre-process to a part of the cores while electric power is supplied thereto and causes electric power supply to another part of cores to be stopped, and for another part of the CPUs, allocates the post-process to at least a part of the cores while electric power is uniformly supplied to the cores.

Abstract: An image processing device includes a plurality of image processors cascaded into a plurality of stages, the image processors each performing image processing on image data received, wherein an image processor other than an image processor in the final stage performs image processing on image data being part of image data input, and transfers the remaining image data to an image processor in a subsequent stage.

Abstract: An image forming apparatus includes: a first memory for temporarily storing therein image data output to an image forming unit; a data processing processor for reading the image data; a second memory for temporarily storing therein the image data; and a main processor for causing the data processing processor to sequentially read the image data, wherein the data processing processor includes: data transfer units; a transfer control unit; and a table, the main processor sets a start address and a size and instructs the transfer control unit to activate the data transfer units, the transfer control unit divides a size of image data and sets a start address and a size of divided image data, the data transfer units read corresponding image data and output it to the second memory, and the transfer control unit subsequently controls the data transfer units and notifies the transfer completion to the main processor.

Abstract: An image forming apparatus includes a hardware processor including CPUs each including cores, a process being executed by the CPUs, wherein the hardware processor managing the cores causes a first process or a second process to be executed, when the first process is executed, while electric power is uniformly supplied to the cores, allocates a pre-process in which sequential processing is performed to a part of the cores and a post-process in which parallel processing is performed to another part of cores, and when the second process is executed, for a part of the CPUs, allocates the pre-process to a part of the cores while electric power is supplied thereto and causes electric power supply to another part of cores to be stopped, and for another part of the CPUs, allocates the post-process to at least a part of the cores while electric power is uniformly supplied to the cores.

Abstract: An image processing device includes a plurality of image processors cascaded into a plurality of stages, the image processors each performing image processing on image data received, wherein an image processor other than an image processor in the final stage performs image processing on image data being part of image data input, and transfers the remaining image data to an image processor in a subsequent stage.

Abstract: An image forming apparatus includes: a first memory for temporarily storing therein image data output to an image forming unit; a data processing processor for reading the image data; a second memory for temporarily storing therein the image data; and a main processor for causing the data processing processor to sequentially read the image data, wherein the data processing processor includes: data transfer units; a transfer control unit; and a table, the main processor sets a start address and a size and instructs the transfer control unit to activate the data transfer units, the transfer control unit divides a size of image data and sets a start address and a size of divided image data, the data transfer units read corresponding image data and output it to the second memory, and the transfer control unit subsequently controls the data transfer units and notifies the transfer completion to the main processor.

Abstract: If a defect flag stored in a CF 19 while a BIOS is being booted, an information processing device 10 boots a second program stored in an external device 31 connected to a connection section 21, and if the defect flag is not detected, the information processing device 10 confirms whether or not the first program is bootable. If the first program is confirmed to be bootable, the first program is booted and if not, the defect flag is set in the CF 19 and the power of the information processing apparatus 10 is turned off.

Abstract: An image processing apparatus comprises a memory; a store control section to divide and store image data in plural vacant memory regions in the memory; and an image administrating information registering section to register each divided image data divided by the store control section by correlating position information of each divided image data in the image data before dividing the image data with storing position information of each divided image data indicating a storing memory region.

Abstract: An information processing apparatus including: a first recording medium which stores a first program; a connection section which is capable of connecting to a second recording medium outside of the information processing apparatus; an instruction input section to input, while the information processing apparatus is in an activated state, an instruction for booting a second program stored in the second recording medium that is connected to the connection section on booting of the BIOS; and a controller which, performs a check when booting of a BIOS, if the second recording medium is connected and the instruction has been input while the information processing apparatus is in an activated state; in case when the second recording medium is connected and the instruction has been input is confirmed, the control section boots the second program; and in case when it is not confirmed, the control section boots the first program.

Abstract: A data processing apparatus which saves data in a volatile memory into a nonvolatile memory when power is off, the data processing apparatus including: a detecting circuit for outputting a momentary interruption detecting signal when a power source voltage is below a first threshold voltage, and a power failure detecting signal when the power source voltage is below a second threshold voltage that is lower than the first threshold voltage; and a control section adapted to start saving of the data in the volatile memory into the nonvolatile memory when the detecting circuit has output the momentary interruption detecting signal, continue save of the data, and carry out a predetermined shutdown processing when the detecting circuit has output the power failure detecting signal after the detecting circuit has output the momentary interruption detecting signal.

Abstract: An information processing apparatus including: a first recording medium which stores a first program; a connection section which is capable of connecting with a second recording medium from outside; and a controller which determines, during BIOS boot-up operation, whether or not the connection section is connected with the second recording medium which stores predetermined authentication information, and if connected, boots a second program stored in the second recording medium, while if not connected, boots the first program stored in the first recording medium.

Abstract: A memory apparatus including: a cache control section to control a cache memory for an auxiliary storage apparatus; a volatile memory; and a nonvolatile memory, wherein the cache memory for the auxiliary storage apparatus is configured to have a volatile cache memory provided in the volatile memory and a nonvolatile cache memory provided in the nonvolatile memory, and wherein the cache control section accesses the nonvolatile cache memory using a write back method.

Abstract: An information processing apparatus including: a nonvolatile memory; a volatile system memory in which predetermined data stored in the nonvolatile memory is developed; a control section to save the predetermined data stored in the system memory in the nonvolatile memory when a start of power-off operation is detected; and a storage section that stores a first timing information representing a time point of terminating the operation of saving the predetermined data in the nonvolatile memory, and a second timing information representing a power-off time point, wherein the control section compares the first timing information stored in the storage section with the second timing information, subsequent to the next operation of turning on of the power.

Abstract: An image processing apparatus comprises an input section which inputs a user identification information; and a registration section which registers an image data in association with the user identification information.

Abstract: A memory administrating method of administrating a memory divided into plural regions each of which consists of consecutive memory addresses, where the method includes the steps of: providing each region of the plural regions with usage information; and when releasing a release target region currently in use, determining usage of the release target region based on the usage information of at least one of neighboring regions positioned before and after the release target region.

Abstract: An information processing apparatus including: a first recording medium which stores a first program; a connection section which is capable of connecting to a second recording medium outside of the information processing apparatus; an instruction input section to input, while the information processing apparatus is in an activated state, an instruction for booting a second program stored in the second recording medium that is connected to the connection section on booting of the BIOS; and a controller which, performs a check when booting of a BIOS, if the second recording medium is connected and the instruction has been input while the information processing apparatus is in an activated state; in case when the second recording medium is connected and the instruction has been input is confirmed, the control section boots the second program; and in case when it is not confirmed, the control section boots the first program.

Abstract: If a defect flag stored in a CF 19 while a BIOS is being booted, an information processing device 10 boots a second program stored in an external device 31 connected to a connection section 21, and if the defect flag is not detected, the information processing device 10 confirms whether or not the first program is bootable. If the first program is confirmed to be bootable, the first program is booted and if not, the defect flag is set in the CF 19 and the power of the information processing apparatus 10 is turned off.

Abstract: An information processing apparatus including: a first recording medium which stores a first program; a connection section which is capable of connecting with a second recording medium from outside; and a controller which determines, during BIOS boot-up operation, whether or not the connection section is connected with the second recording medium which stores predetermined authentication information, and if connected, boots a second program stored in the second recording medium, while if not connected, boots the first program stored in the first recording medium.