Patents by Inventor Munetoshi Eguchi

Munetoshi Eguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080086587
    Abstract: A data save apparatus including: a system memory, in which a plurality of segment regions having uneven capacities are provided; a nonvolatile memory, into which data having been memorized in the system memory are saved; and a controller which controls to save data with a unit of each of the segment regions into the nonvolatile memory from the system memory, wherein the controller determines whether saving data of each of the segment regions into the nonvolatile memory is necessary, and when a total capacity of segment regions, data in which having been determined to be necessary to be saved, reaches to a prescribed value, the controller transfers the data of the segment regions determined to be necessary to be saved into the nonvolatile memory by a DMA (Direct Memory Access) mode in descending order of segment region capacity.
    Type: Application
    Filed: October 5, 2007
    Publication date: April 10, 2008
    Inventors: Munetoshi EGUCHI, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Kenji Okuyama
  • Publication number: 20080086586
    Abstract: An information processing apparatus including: a nonvolatile memory; a volatile system memory in which predetermined data stored in the nonvolatile memory is developed; a control section to save the predetermined data stored in the system memory in the nonvolatile memory when a start of power-off operation is detected; and a storage section that stores a first timing information representing a time point of terminating the operation of saving the predetermined data in the nonvolatile memory, and a second timing information representing a power-off time point, wherein the control section compares the first timing information stored in the storage section with the second timing information, subsequent to the next operation of turning on of the power.
    Type: Application
    Filed: October 3, 2007
    Publication date: April 10, 2008
    Inventors: Tomoya Ogawa, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Fumikage Uchida, Nao Moromizato, Munetoshi Eguchi, Kenji Okuyama
  • Publication number: 20080086659
    Abstract: A data processing apparatus which saves data in a volatile memory into a nonvolatile memory when power is off, the data processing apparatus including: a detecting circuit for outputting: a momentary interruption detecting signal when a power source voltage is below a first threshold voltage, and a power failure detecting signal when the power source voltage is below a second threshold voltage that is lower than the first threshold voltage; and a control section adapted to start saving of the data in the volatile memory into the nonvolatile memory when the detecting circuit has output the momentary interruption detecting signal, continue save of the data, and carry out a predetermined shutdown processing when the detecting circuit has output the power failure detecting signal after the detecting circuit has output the momentary interruption detecting signal.
    Type: Application
    Filed: October 3, 2007
    Publication date: April 10, 2008
    Inventors: Tetsuya Ishikawa, Tomohiro Suzuki, Yuji Tamura, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Munetoshi Eguchi, Kenji Okuyama
  • Publication number: 20070271408
    Abstract: A memory administrating method of administrating a memory divided into plural regions each of which consists of consecutive memory addresses, comprising steps of: providing each region of the plural regions with usage information; and when releasing a release target region currently being in use, determining a usage of the release target region based on the usage information of at least one of neighboring regions positioned before and after the release target region.
    Type: Application
    Filed: February 15, 2007
    Publication date: November 22, 2007
    Inventors: Hiroyasu Nishimura, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Masayuki Yasukaga, Munetoshi Eguchi
  • Publication number: 20070269138
    Abstract: An image processing apparatus comprises a memory; a store control section to divide and store image data in plural vacant memory regions in the memory; and an image administrating information registering section to register each divided image data divided by the store control section by correlating position information of each divided image data in the image data before dividing the image data with storing position information of each divided image data indicating a storing memory region.
    Type: Application
    Filed: March 7, 2007
    Publication date: November 22, 2007
    Inventors: Munetoshi Eguchi, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Masayuki Yasukaga
  • Publication number: 20070271419
    Abstract: A memory administrating method of administrating a memory divided into plural memory regions each of which consists of consecutive memory addresses, comprises steps of: acquiring a memory region from the plural memory regions; and registering at least one of usage information indicating the usage of the acquired memory region and time period information indicating the using time period for using the acquired memory region in an administrating portion of the acquired memory region.
    Type: Application
    Filed: February 15, 2007
    Publication date: November 22, 2007
    Inventors: Masayuki Yasukaga, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Munetoshi Eguchi
  • Publication number: 20070073911
    Abstract: To provide a system capable of avoiding an apparatus anomaly such as a system hang, even when an anomaly condition of connection in the cable connecting the apparatuses occurs. A first apparatus 10 in the transmission side includes: a data processing device 12; a buffer register 22 in which the processing device writes the data to be sent; a transmission section 23 for sending the data stored in the buffer register to a second apparatus 40 connected by a cable 3; and a loop detection section 27 for detecting an anomaly condition of connection in the cable during the data transmission. When detecting the anomaly condition of connection in the loop detection section, the first apparatus clears the buffer register to release the processing device from the data writing waiting, and at the same time the first apparatus notifies the processing device of the occurrence of the anomaly condition.
    Type: Application
    Filed: February 2, 2006
    Publication date: March 29, 2007
    Inventors: Munetoshi Eguchi, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Masayuki Yasukaga
  • Publication number: 20060282466
    Abstract: An image processing apparatus comprises an input section which inputs a user identification information; and a registration section which registers an image data in association with the user identification information.
    Type: Application
    Filed: October 21, 2005
    Publication date: December 14, 2006
    Applicant: Konica Minolta Business Technologies, Inc.
    Inventors: Masayuki Yasukaga, Tomohiro Suzuki, Yuji Tamura, Tetsuya Ishikawa, Hiroyasu Nishimura, Tomoya Ogawa, Fumikage Uchida, Nao Moromizato, Munetoshi Eguchi