Abstract: Interlaced bi-sensor super-resolution enhancement techniques and a resultant scalable pixel array suitable for a mega-pixel design are disclosed. The method includes interlacing a first array of pixels of a first size with a second array of pixels of a second size. The interlacing of the first array of pixels with the second array of pixels avoids crossing two or more photosensitive areas of the first array of pixels and the second array of pixels.

Abstract: Interlaced bi-sensor super-resolution enhancement techniques and a resultant scalable pixel array suitable for a mega-pixel design are disclosed. The method includes interlacing a first array of pixels of a first size with a second array of pixels of a second size. The interlacing of the first array of pixels with the second array of pixels avoids crossing two or more photosensitive areas of the first array of pixels and the second array of pixels.

Abstract: Example apparatuses are provided for simultaneous generation of high intensity light and modulated light signals at low modulation bias operating characteristics. An example apparatus includes a semipolar or nonpolar GaN-based substrate, a reverse-biased waveguide modulator section, and a forward-biased gain section based on InGaN/GaN quantum-well active regions, wherein the forward-biased gain section is grown on the semipolar or nonpolar GaN-based substrate. Methods of manufacturing the apparatuses described herein are also contemplated and described herein.

Abstract: Interlaced bi-sensor super-resolution enhancement techniques and a resultant scalable pixel array suitable for a mega-pixel design are disclosed. The method includes interlacing a first array of pixels of a first size with a second array of pixels of a second size. The interlacing of the first array of pixels with the second array of pixels avoids crossing two or more photosensitive areas of the first array of pixels and the second array of pixels.

Abstract: Interlaced bi-sensor super-resolution enhancement techniques and a resultant scalable pixel array suitable for a mega-pixel design are disclosed. The method includes interlacing a first array of pixels of a first size with a second array of pixels of a second size. The interlacing of the first array of pixels with the second array of pixels avoids crossing two or more photosensitive areas of the first array of pixels and the second array of pixels.

Abstract: Interlaced bi-sensor super-resolution enhancement techniques and a resultant scalable pixel array suitable for a mega-pixel design are disclosed. The method includes interlacing a first array of pixels of a first size with a second array of pixels of a second size. The interlacing of the first array of pixels with the second array of pixels avoids crossing two or more photosensitive areas of the first array of pixels and the second array of pixels.

Abstract: Interlaced bi-sensor super-resolution enhancement techniques and a resultant scalable pixel array suitable for a mega-pixel design are disclosed. The method includes interlacing a first array of pixels of a first size with a second array of pixels of a second size. The interlacing of the first array of pixels with the second array of pixels avoids crossing two or more photosensitive areas of the first array of pixels and the second array of pixels.

Abstract: Interlaced bi-sensor super-resolution enhancement techniques and a resultant scalable pixel array suitable for a mega-pixel design are disclosed. The method includes interlacing a first array of pixels of a first size with a second array of pixels of a second size. The interlacing of the first array of pixels with the second array of pixels avoids crossing two or more photosensitive areas of the first array of pixels and the second array of pixels.

Abstract: A method, an apparatus and/or a system of injection locking based power amplifier is disclosed. A method includes inputting a reference signal through an injection circuit of an oscillator circuit that generates an output signal of high power that oscillates at an inherent frequency of oscillation of the oscillator circuit. The method also includes reducing a frequency of the reference signal through a differential transistor pair coupled to the injection circuit of the oscillator circuit. The method further includes locking through a tuning circuit of the oscillator circuit coupled to the differential transistor pair a frequency of the output signal to the reduced frequency of the reference signal based on the power of the reference signal to amplify the power of the reference signal through the oscillator circuit. The frequency of the reference signal is higher than the frequency of the output signal.

Abstract: A method and apparatus of coordinated in-pixel light detection is provided. In one aspect, the method includes implementing an N-number of avalanche photodiodes inside a pixel circuit of a light detection circuit. The method also includes coordinating an output of the N-number of avalanche photodiodes through a counter circuit. The method further includes reducing a deadtime of the light detection circuit by a factor of ‘N’ through the N-number of avalanche photodiodes and the counter circuit operating in concert. The method furthermore includes measuring an intensity of a light through the light detection circuit. N-number of avalanche photodiodes is in a common well of a semiconductor technology. N-number of avalanche photodiodes is fabricated on a deep submicron semiconductor technology. A fill factor of the pixel circuit improves and a deadtime reduces through fabrication of the avalanche photodiodes in a common well. Also, a photon count rate increases through reducing the deadtime.

Abstract: A single photon counting image sensor and method is provided. In one aspect, the method of an image sensor includes counting through a counter circuit a number of photons detected through a photodiode when a light is incident on the photodiode. The method also includes storing in a memory circuit a time a count of the number of photons take to match a reference count of the number of photons. In another aspect, an image sensor device includes a pixel circuit. The image sensor device also includes a photodiode circuit of the pixel circuit to detect photons when a light is incident on the photodiode circuit. The image sensor device further includes a counter circuit of the pixel circuit coupled to the photodiode circuit to count a number of photons detected when a light is incident on the avalanche photo diode.

Abstract: A high speed analog photon counter and method is provided. In one aspect, the method includes accumulating an electric charge in a capacitor of a circuit electrically coupled to a current source. The method further includes comparing the electric charge accumulated in the capacitor of the circuit with a reference voltage through a comparator of the circuit electrically coupled to an output of the capacitor. The method also includes increasing a speed of operation of a measurement device through implementing the circuit inside a pixel. The method further includes transferring the accumulated electric charge to a circuit of an adjacent pixel and synchronizing the transfer of the accumulated electric with a movement of an object captured by an image sensor device before implementing a time-delay integration operation.

Abstract: Disclosed are a system, a method and an apparatus of reduction of delay between subsequent capture operations of a light-detection device. In one embodiment, a light-detection circuit includes an avalanche photodiode implemented in a deep submicron CMOS technology. In addition, the light-detection circuit includes a passive quench control circuit to create an avalanche current that generates a high voltage at an output of a second inverter gate of the circuit. The light-detection circuit further includes an active quench control circuit to reduce a dead time of the circuit. The light-detection circuit also includes a reset circuit to create a low voltage at an output of the second inverter gate and to create an active reset through a PMOS transistor of the light-detection circuit.

Abstract: A high speed analog photon counter and method is provided. In one aspect, the method includes delivering an electric charge to a circuit of the high speed analog photon counter through a current source of the circuit. The method also includes accumulating the electric charge in a capacitor of the circuit electrically coupled to the current source. The method further includes comparing the electric charge accumulated in the capacitor of the circuit with a reference voltage through a comparator of the circuit electrically coupled to an output of the capacitor. The output of the capacitor of the circuit is coupled to an input of the comparator of the circuit, and the reference voltage is coupled to another input of the comparator of the circuit. The method furthermore includes resetting the capacitor of the circuit when the electric charge accumulated in the capacitor of the circuit matches the reference voltage.

Abstract: A high speed analog photon counter and method is provided. In one aspect, the method includes accumulating an electric charge in a capacitor of a circuit electrically coupled to a current source. The method further includes comparing the electric charge accumulated in the capacitor of the circuit with a reference voltage through a comparator of the circuit electrically coupled to an output of the capacitor. The method also includes increasing a speed of operation of a measurement device through implementing the circuit inside a pixel. The method further includes transferring the accumulated electric charge to a circuit of an adjacent pixel and synchronizing the transfer of the accumulated electric with a movement of an object captured by an image sensor device before implementing a time-delay integration operation.

Abstract: Disclosed are a system, a method and an apparatus of reduction of delay between subsequent capture operations of a light-detection device. In one embodiment, a light-detection circuit includes an avalanche photodiode implemented in a deep submicron CMOS technology. In addition, the light-detection circuit includes a passive quench control circuit to create an avalanche current that generates a high voltage at an output of a second inverter gate of the circuit. The light-detection circuit further includes an active quench control circuit to reduce a dead time of the circuit. The light-detection circuit also includes a reset circuit to create a low voltage at an output of the second inverter gate and to create an active reset through a PMOS transistor of the light-detection circuit.

Abstract: Disclosed are a system, a method and an apparatus of reduction of delay between subsequent capture operations of a light-detection device. In one embodiment, a light-detection circuit includes an avalanche photodiode implemented in a deep submicron CMOS technology. In addition, the light-detection circuit includes a passive quench control circuit to create an avalanche current that generates a high voltage at an output of a second inverter gate of the circuit. The light-detection circuit further includes an active quench control circuit to reduce a dead time of the circuit. The light-detection circuit also includes a reset circuit to create a low voltage at an output of the second inverter gate and to create an active reset through a PMOS transistor of the light-detection circuit.

Abstract: A high speed analog photon counter and method is provided. In one aspect, the method includes delivering an electric charge to a circuit of the high speed analog photon counter through a current source of the circuit. The method also includes accumulating the electric charge in a capacitor of the circuit electrically coupled to the current source. The method further includes comparing the electric charge accumulated in the capacitor of the circuit with a reference voltage through a comparator of the circuit electrically coupled to an output of the capacitor. The output of the capacitor of the circuit is coupled to an input of the comparator of the circuit, and the reference voltage is coupled to another input of the comparator of the circuit. The method furthermore includes resetting the capacitor of the circuit when the electric charge accumulated in the capacitor of the circuit matches the reference voltage.

Abstract: A method, an apparatus and/or a system of complementary differential input based mixer circuit is disclosed. In one aspect, the method includes inputting a single ended signal to a mixer circuit comprising a differential input circuit through a complementary differential transistor pair of the differential input circuit of the mixer circuit. The method also includes converting the signal ended signal to a differential signal through the complementary differential transistor pair of the differential input circuit to drive the mixer circuit.

Abstract: A method, an apparatus and/or a system of injection locking based power amplifier is disclosed. A method includes inputting a reference signal through an injection circuit of an oscillator circuit that generates an output signal of high power that oscillates at an inherent frequency of oscillation of the oscillator circuit. The method also includes reducing a frequency of the reference signal through a differential transistor pair coupled to the injection circuit of the oscillator circuit. The method further includes locking through a tuning circuit of the oscillator circuit coupled to the differential transistor pair a frequency of the output signal to the reduced frequency of the reference signal based on the power of the reference signal to amplify the power of the reference signal through the oscillator circuit. The frequency of the reference signal is higher than the frequency of the output signal.