Abstract: Disclosed herein are system, method, and computer program product embodiments for NR cell prioritization based on carrier bandwidths. An embodiment operates by storing a plurality of neighboring cell frequencies and respective carrier bandwidths of the plurality of neighboring cell frequencies. The embodiment determines whether a carrier bandwidth corresponding to a neighboring cell frequency of the plurality of neighboring cell frequencies is less than a serving cell carrier bandwidth. In response to a determination that the carrier bandwidth corresponding to the neighboring cell frequency is less than the serving cell carrier bandwidth, the embodiment determines a biased signal strength measurement by adding an offset to a signal strength measurement corresponding to the neighboring cell frequency, where the offset is determined based at least in part on a data throughput requirement of the UE.

Abstract: Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.

Abstract: An oil separator is provided and includes an exterior shell defining a first interior and first and second openings fluidly communicative with the first interior, a distributor and first and second filter media cartridges. The distributor is integrated within the exterior shell to define a second interior within the first interior, has a length, which is slightly less than that of the exterior shell, being disposed to define opposite spaces between opposites ends thereof and opposite ends of the exterior shell and is sealed to the exterior shell along the length to form first and second passageways from the first opening to the opposite spaces. The first and second filter media cartridges are disposed within the first interior between the opposite spaces and the second opening.

Abstract: An oil separator to separate oil from oil and refrigerant mixture. The oil separator includes inlets to allow entry of the oil and refrigerant mixture into the oil separator. The mixture flows and strikes on center of the one or more walls of the oil separator. The mixture then flows towards demister pads for filtration. The oil is separated from the mixture and exits the oil separator from the oil outlet. The refrigerant separated from the mixture escapes through the refrigerant outlet.

Abstract: A water-cooled heat exchanger with oil separator having integrated refrigerant distribution, the oil separator, including: an exterior shell having opposite end walls defining a first interior, and a first and second opening fluidly communicative with the first interior; a plurality of baffles operably coupled to and extending from at least a first opposite end wall, each baffle including a first support member generally parallel to a second support member, each operably coupled in a generally perpendicular orientation, to at least the first opposite end wall, and a crossmember operably coupled between a first and second support member, the crossmember having a width dimension that is less than the width of the first support member and the second support member, forming an orifice between the crossmember and the at least first opposite end wall; and a distributor integrated within the exterior shell to define a second interior within the first interior.

Abstract: Various implementations described herein are directed to a device having memory control circuitry having global passgates and a read-write driver that provides a global read-write signal to the global passgates. The device may have sense amplifier circuitry with local-drivers and a sense amplifier driver that provides a sense amplifier enable signal to the local-drivers, wherein the local-drivers may include multiple buffers coupled to the sense amplifier driver in parallel.

Abstract: Various implementations described herein are directed to a device having memory control circuitry having global passgates and a read-write driver that provides a global read-write signal to the global passgates. The device may have sense amplifier circuitry with local-drivers and a sense amplifier driver that provides a sense amplifier enable signal to the local-drivers, wherein the local-drivers may include multiple buffers coupled to the sense amplifier driver in parallel.

Abstract: Various implementations described herein are related to a device with a wordline driver that provides a wordline signal to a wordline based on a row selection signal and a row clock signal. The device may have row selector logic that provides the row selection signal to the wordline driver based on first input signals in a periphery voltage domain. The device may also have level shifter circuitry that provides the row clock signal to the wordline driver in a core voltage domain based on second input signals in the periphery voltage domain.

Abstract: Various implementations described herein are related to a device with a wordline driver that provides a wordline signal to a wordline based on a row selection signal and a row clock signal. The device may have row selector logic that provides the row selection signal to the wordline driver based on first input signals in a periphery voltage domain. The device may also have level shifter circuitry that provides the row clock signal to the wordline driver in a core voltage domain based on second input signals in the periphery voltage domain.

Abstract: Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.

Abstract: A multi-compartment negative air filtration system and a method of operating a multi-compartment negative air filtration system are provided. The multi-compartment negative air filtration system includes a housing including a first compartment and a second compartment. The first compartment and the second compartment separated by at least one panel member. Each of the first compartment and the second compartment including an inlet, an outlet, a pre-filter disposed downstream of the inlet, a HEPA filter disposed downstream of the pre-filter, an a fan assembly disposed downstream of the HEPA filter, the fan assembly in airflow communication with the pre-filter and the HEPA filter, the fan assembly generating a negative pressure across the pre-filter and the HEPA filter.

Abstract: A joint assembly comprising a first cup and a second cup for joining a first pipe and a second pipe. The first and the second pipes have an offset in a three-dimensional space having ‘x’, ‘y’, and ‘z’ dimensions, where the longitudinal axes of the first and the second pipes are in the ‘z’ dimension. The first cup and the second cup are adapted to join the first pipe with the second pipe by compensating for the offset in the ‘x’, ‘y’, and ‘z’ dimensions.

Abstract: A water-cooled heat exchanger with oil separator having integrated refrigerant distribution, the oil separator, including: an exterior shell having opposite end walls defining a first interior, and a first and second opening fluidly communicative with the first interior; a plurality of baffles operably coupled to and extending from at least a first opposite end wall, each baffle including a first support member generally parallel to a second support member, each operably coupled in a generally perpendicular orientation, to at least the first opposite end wall, and a crossmember operably coupled between a first and second support member, the crossmember having a width dimension that is less than the width of the first support member and the second support member, forming an orifice between the crossmember and the at least first opposite end wall; and a distributor integrated within the exterior shell to define a second interior within the first interior.

Abstract: Various implementations described herein are related to a device having memory circuitry and multiplexer circuitry. The memory circuitry may include a single bank of memory cells that are arranged in multiple columns, and each column of the multiple columns may provide singe-bit data. The multiplexer circuitry may include multiplexer logic that receives the single-bit data from each column of the multiple columns and provides selected data as output data.

Abstract: An oil separator to separate oil from oil and refrigerant mixture. The oil separator includes inlets to allow entry of the oil and refrigerant mixture into the oil separator. The mixture flows and strikes on center of the one or more walls of the oil separator. The mixture then flows towards demister pads for filtration. The oil is separated from the mixture and exits the oil separator from the oil outlet. The refrigerant separated from the mixture escapes through the refrigerant outlet.

Abstract: An oil separator is provided and includes an exterior shell defining a first interior and first and second openings fluidly communicative with the first interior, a distributor and first and second filter media cartridges. The distributor is integrated within the exterior shell to define a second interior within the first interior, has a length, which is slightly less than that of the exterior shell, being disposed to define opposite spaces between opposites ends thereof and opposite ends of the exterior shell and is sealed to the exterior shell along the length to form first and second passageways from the first opening to the opposite spaces. The first and second filter media cartridges are disposed within the first interior between the opposite spaces and the second opening.

Abstract: Various implementations described herein are related to a device having memory circuitry and multiplexer circuitry. The memory circuitry may include a single bank of memory cells that are arranged in multiple columns, and each column of the multiple columns may provide singe-bit data. The multiplexer circuitry may include multiplexer logic that receives the single-bit data from each column of the multiple columns and provides selected data as output data.

Abstract: According to one implementation of the present disclosure, an integrated circuit includes first and second word-line decoder circuitry, two or more memory instances coupled to the first and second word-line decoder circuitry; and a control block circuitry coupled to the first and second word-line decoder circuitry and the two or more memory instances. Also, a pin bus enabled in the control block circuitry may be configured to at least partially control selection of one or more of the two or more memory instances.

Abstract: Various implementations described herein are directed to memory circuitry having an array of bitcells and bitlines coupled to columns of the bitcells. Also, column decoder circuitry may be coupled to the bitcells via the bitlines, and the column decoder circuitry may have read logic coupled to an output node. The column decoder circuitry may have select logic coupled between a voltage supply and the read logic. Enable signals may be used to activate the select logic to pass the voltage supply to the read logic, and the bitlines provide bitline signals that activate the read logic to pass the voltage supply from the select logic to the output node.

Abstract: Various implementations described herein are directed to memory circuitry having an array of bitcells and bitlines coupled to columns of the bitcells. Also, column decoder circuitry may be coupled to the bitcells via the bitlines, and the column decoder circuitry may have read logic coupled to an output node. The column decoder circuitry may have select logic coupled between a voltage supply and the read logic. Enable signals may be used to activate the select logic to pass the voltage supply to the read logic, and the bitlines provide bitline signals that activate the read logic to pass the voltage supply from the select logic to the output node.