Patents by Inventor Munish Kumar

Munish Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10978141
    Abstract: According to one implementation of the present disclosure, an integrated circuit includes first and second word-line decoder circuitry, two or more memory instances coupled to the first and second word-line decoder circuitry; and a control block circuitry coupled to the first and second word-line decoder circuitry and the two or more memory instances. Also, a pin bus enabled in the control block circuitry may be configured to at least partially control selection of one or more of the two or more memory instances.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: April 13, 2021
    Assignee: Arm Limited
    Inventors: Yew Keong Chong, Sriram Thyagarajan, Andy Wangkun Chen, Vivek Asthana, Munish Kumar
  • Patent number: 10878893
    Abstract: Various implementations described herein are directed to memory circuitry having an array of bitcells and bitlines coupled to columns of the bitcells. Also, column decoder circuitry may be coupled to the bitcells via the bitlines, and the column decoder circuitry may have read logic coupled to an output node. The column decoder circuitry may have select logic coupled between a voltage supply and the read logic. Enable signals may be used to activate the select logic to pass the voltage supply to the read logic, and the bitlines provide bitline signals that activate the read logic to pass the voltage supply from the select logic to the output node.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: December 29, 2020
    Assignee: Arm Limited
    Inventors: Vianney Antoine Choserot, Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Munish Kumar
  • Publication number: 20200388329
    Abstract: Various implementations described herein are directed to memory circuitry having an array of bitcells and bitlines coupled to columns of the bitcells. Also, column decoder circuitry may be coupled to the bitcells via the bitlines, and the column decoder circuitry may have read logic coupled to an output node. The column decoder circuitry may have select logic coupled between a voltage supply and the read logic. Enable signals may be used to activate the select logic to pass the voltage supply to the read logic, and the bitlines provide bitline signals that activate the read logic to pass the voltage supply from the select logic to the output node.
    Type: Application
    Filed: June 4, 2019
    Publication date: December 10, 2020
    Inventors: Vianney Antoine Choserot, Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Munish Kumar
  • Publication number: 20200351373
    Abstract: A computer-implemented method comprising extracting profile information for a profile, converting the profile information into a readable file format, and storing the converted profile information. The method may include creating a database file from the converted profile information and copying the database file. The method may include updating the database file copy with profile changes, and loading the updated database file copy to generate an updated profile where the updated database file copy is mapped according to metadata in the updated database file copy. The method may include altering a profile pointer reference to point to the updated database file copy to activate the updated profile, wherein activating the at least one updated profile activates the one or more profile changes.
    Type: Application
    Filed: May 3, 2019
    Publication date: November 5, 2020
    Inventors: Munish Kumar Gupta, Rohit Prakash More
  • Patent number: 10763267
    Abstract: Various implementations described herein refer to an integrated circuit having a memory structure with a two-bitcell layout and a four cell poly pitch. The two-bitcell layout includes a first bitcell and a second bitcell with structural contours that are joined together in a coupling arrangement. The first bitcell and the second bitcell have multiple transistors that are arranged to store data during write operations and allow access of data during read operations.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: September 1, 2020
    Assignee: Arm Limited
    Inventors: Yew Keong Chong, Sriram Thyagarajan, Munish Kumar
  • Patent number: 10744492
    Abstract: A process is provided for removing contaminants from olefin containing C4 streams. The streams are contacted with an X based zeolite adsorbent comprising greater than 88% X zeolite at a SiO2/Al2O3 ratio of less than 2.5 and an alkali metal salt present in excess of an amount required to achieve full exchange of cation sites on the X based zeolite. The resulting alkali oxide on a volatile free basis is less than 1% (by mass) of the X based adsorbent. The contaminants that are removed include sulfur, oxygenate, and nitrogen based contaminants.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 18, 2020
    Assignee: UOP LLC
    Inventors: Stephen R. Caskey, Munish Kumar Sharma, Jayant K. Gorawara, Pijus Kanti Roy, Frank S. Modica
  • Publication number: 20200219890
    Abstract: Various implementations described herein refer to an integrated circuit having a memory structure with a two-bitcell layout and a four cell poly pitch. The two-bitcell layout includes a first bitcell and a second bitcell with structural contours that are joined together in a coupling arrangement. The first bitcell and the second bitcell have multiple transistors that are arranged to store data during write operations and allow access of data during read operations.
    Type: Application
    Filed: January 9, 2019
    Publication date: July 9, 2020
    Inventors: Yew Keong Chong, Sriram Thyagarajan, Munish Kumar
  • Publication number: 20200023341
    Abstract: A process is provided for removing contaminants from olefin containing C4 streams. The streams are contacted with an X based zeolite adsorbent comprising greater than 88% X zeolite at a SiO2/Al2O3 ratio of less than 2.5 and an alkali metal salt present in excess of an amount required to achieve full exchange of cation sites on the X based zeolite. The resulting alkali oxide on a volatile free basis is less than 1% (by mass) of the X based adsorbent. The contaminants that are removed include sulfur, oxygenate, and nitrogen based contaminants.
    Type: Application
    Filed: November 3, 2017
    Publication date: January 23, 2020
    Inventors: Stephen R. Caskey, Munish Kumar Sharma, Jayant K. Gorawara, Pijus Kanti Roy, Frank S. Modica
  • Publication number: 20190132958
    Abstract: System and method of producing on-demand three-dimensional (3D) printed devices on flexible substrates such as paper, plastic, or polymer using metal alloy nanopowders at low temperatures of printing in the range of 150 degrees Celsius (C) to 300 degrees C. The printer disclosed herein may employ a computer-aided design graphics file given as an input to the printer. The printer will selectively release and print the metal alloy nanopowders on select areas on the substrate to form a conductive pattern.
    Type: Application
    Filed: October 26, 2018
    Publication date: May 2, 2019
    Inventors: Munish Kumar SHARMA, Chidambaram SP
  • Publication number: 20190018756
    Abstract: An execution trace of an application program comprises a sequence of ordered programming instructions generated during execution of the application program indicating an execution flow of the application program. The sequence of ordered programming instructions is partitioned into a plurality of linked code segments comprising first and second code segments. The first code segment comprises a terminating programming instruction that terminates the first code segment and links the first code segment to an initial programming instruction of the second code segment. A directed graph representing the execution flow of the application program between the plurality of linked code segments is generated. The directed graph comprises a plurality of linked nodes representing the plurality of linked code segments. The directed graph is output to a graphical user interface (GUI) for display.
    Type: Application
    Filed: August 30, 2018
    Publication date: January 17, 2019
    Inventor: Munish Kumar
  • Publication number: 20180285248
    Abstract: Embodiments of present disclosure disclose efficient system and method for identifying operational process associated with UI of enterprise based on inputs from user and automatic generating one or more test scripts for testing of operational process. System discloses to directly capture inputs from UI by configuring URL of UI to system. Method includes capturing at least one of, one or more elements, one or more labels associated with each of one or more elements, from UI and one or more error conditions associated with one or more elements. Upon capturing, one or more attributes are identified from plurality of attributes based on mapping of one or more labels with plurality of attributes and further operational process is identified from plurality of operational processes based on one or more attributes. One or more test scripts are generated for identified operational process based on metadata associated with operational process.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventor: Munish Kumar Gupta
  • Publication number: 20180287914
    Abstract: System and method for management of applications and services in a cloud environment are described. The method includes receiving a plurality of configurations and rules for the plurality of services in the cloud environment. A collector is initialized based on the plurality of configurations and rules related to the plurality of services. The collector collects run time data of the plurality of services. Further, runtime data is compared with the plurality of configurations and rules. Based on the comparison an event is triggered responsive to a deviation in runtime data with respect to the plurality of configurations and rules. Furthermore, one or more actuator services are determined corresponding to the triggered event for handling the triggered event.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 4, 2018
    Inventor: Munish Kumar Gupta
  • Patent number: 10067853
    Abstract: An execution trace of an application program comprises a sequence of ordered programming instructions generated during execution of the application program indicating an execution flow of the application program. The sequence of ordered programming instructions is partitioned into a plurality of linked code segments comprising first and second code segments. The first code segment comprises a terminating programming instruction that terminates the first code segment and links the first code segment to an initial programming instruction of the second code segment. A directed graph representing the execution flow of the application program between the plurality of linked code segments is generated. The directed graph comprises a plurality of linked nodes representing the plurality of linked code segments. The directed graph is output to a graphical user interface (GUI) for display.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: September 4, 2018
    Assignee: CA, Inc.
    Inventor: Munish Kumar
  • Patent number: 9997217
    Abstract: Various implementations described herein are directed to an integrated circuit having core circuitry with an array of memory cells arranged in columns. The integrated circuit may include write assist circuitry having a column selector that accesses the memory cells via a bitline coupled to each of the columns. The write assist circuitry may include a first node that couples the column selector to a discharge circuit and a feedback circuit. The write assist circuitry may include a second node that couples a trigger circuit to the discharge circuit and the feedback circuit. The trigger circuit enables the discharge circuit, discharges the second node, and is disabled after discharging the second node. The discharge circuit discharges the first node, and the feedback circuit tracks the first node and disables the discharge circuit.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: June 12, 2018
    Assignee: ARM Limited
    Inventors: Ankur Goel, Munish Kumar, Nitin Jindal, Rahul Mathur, Shruti Aggarwal, Bikas Maiti, Yew Keong Chong
  • Publication number: 20180137566
    Abstract: Embodiments of the present invention are directed to a system and method for a no-click institutional allocation platform that automatically matches at least two transactions. The system and method may import at least one customer side allocation and at least one broker-dealer firm-side transaction from an external system using a transaction import engine. The system and method process the imported transactions using the transaction matching engine by matching at least one customer-side allocation to at least one broker-dealer firm side transaction. The system and method may also have the capability to handle any exceptions using an exception handling engine. If the exception is successfully handled or there is no exception, the system and method then automatically settle the matched transaction using a step-out processing engine. The details of the settled transaction are then displayed to a user using a transaction visualization engine.
    Type: Application
    Filed: October 28, 2013
    Publication date: May 17, 2018
    Applicant: JPMorgan Chase Bank, N.A.
    Inventors: Kent A. Paschal, Ioannis Vasmatzidis, Munish Kumar, Satyajit Roy Choudhury, Danny Ljungberg
  • Publication number: 20170270026
    Abstract: An execution trace of an application program comprises a sequence of ordered programming instructions generated during execution of the application program indicating an execution flow of the application program. The sequence of ordered programming instructions is partitioned into a plurality of linked code segments comprising first and second code segments. The first code segment comprises a terminating programming instruction that terminates the first code segment and links the first code segment to an initial programming instruction of the second code segment. A directed graph representing the execution flow of the application program between the plurality of linked code segments is generated. The directed graph comprises a plurality of linked nodes representing the plurality of linked code segments. The directed graph is output to a graphical user interface (GUI) for display.
    Type: Application
    Filed: March 15, 2016
    Publication date: September 21, 2017
    Inventor: Munish Kumar
  • Patent number: 9411741
    Abstract: The disclosure generally relates to methods and systems for application level caching and more particularly to dynamically applying caching policies to a software application. In one embodiment, an application level caching method, comprising: monitoring, using a utility executed by a processor, run-time data access operations corresponding to an application; identifying, using the processor, at least one characteristic associated with the run-time data access operations; triggering, using the processor, a caching rule based on the at least one characteristic associated with the run-time data access operations; and providing, using the processor, a memory access instruction according to the caching rule.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: August 9, 2016
    Assignee: WIPRO LIMITED
    Inventors: Munish Kumar Gupta, Aravind Ajad Yarra
  • Publication number: 20150186133
    Abstract: This disclosure relates generally to information technology management, and more particularly to systems and methods for enterprise application portfolio management. In one embodiment, an application portfolio management system is disclosed, comprising: a hardware processor; and a memory storing processor-executable instructions for: receiving application usage data associated with software applications utilized by a plurality of users; obtaining computer program instructions for processing the application usage data; processing the application usage data according to the computer program instructions, to generate a recommendation for one or more maintenance operations associated with one or more of the applications; and providing the generated recommendation.
    Type: Application
    Filed: February 20, 2014
    Publication date: July 2, 2015
    Applicant: WIPRO LIMITED
    Inventors: Aravind Ajad Yarra, Munish Kumar Gupta
  • Publication number: 20150032966
    Abstract: The disclosure generally relates to methods and systems for application level caching and more particularly to dynamically applying caching policies to a software application. In one embodiment, an application level caching method, comprising: monitoring, using a utility executed by a processor, run-time data access operations corresponding to an application; identifying, using the processor, at least one characteristic associated with the run-time data access operations; triggering, using the processor, a caching rule based on the at least one characteristic associated with the run-time data access operations; and providing, using the processor, a memory access instruction according to the caching rule.
    Type: Application
    Filed: September 18, 2013
    Publication date: January 29, 2015
    Applicant: Wipro Limited
    Inventors: Munish Kumar Gupta, Aravind Ajad Yarra
  • Publication number: 20110009362
    Abstract: Solubility-enhanced forms of aprepitant and processes for preparing such forms. The invention also provides solubility-enhanced forms of aprepitant that also possess stability against solid state conversions. Certain solubility-enhanced forms of aprepitant comprise a cyclodextrin or any of its derivatives. Other solubility-enhanced forms of aprepitant comprise fine particle preparations of aprepitant. The invention further provides non-nanoparticulate pharmaceutical formulations prepared using solubility-enhanced forms of aprepitant. The invention also provides taste-masked and orally disintegrating pharmaceutical formulations comprising aprepitant. Further, pharmaceutical formulations comprising solubilityenhanced forms of aprepitant and processes of preparation of such formulations, as well as methods of using them are provided.
    Type: Application
    Filed: February 27, 2009
    Publication date: January 13, 2011
    Applicants: DR. REDDY'S LABORATORIES LTD., DR. REDDY'S LABORATORIES, INC.
    Inventors: Mahendra Ramachandra Joshi, Nithya Radhakrishnan, Munish Kumar Dhiman, Pradeep Jairao Karatgi, Sanjay Chhagan Wagh, Raviraj Sukumar Pillai, Harshal Prabhakar Bhagwatwar, Venkata Nookaraju Sreedharala