Patents by Inventor Murali Narasimhan
Murali Narasimhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11971741Abstract: Aspects of the present disclosure control aging of a signal path in an idle mode to mitigate aging. In one example, an input of the signal path is alternately parked low and high over multiple idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, a clock signal (e.g., a clock signal with a low frequency) is input to the signal path during idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, the input of the signal path is parked high or low during each idle period based on an aging pattern.Type: GrantFiled: August 6, 2021Date of Patent: April 30, 2024Assignee: QUALCOMM INCORPORATEDInventors: Mukund Narasimhan, Murali Krishna Ade, Arun David Arul Diraviyam, Mayank Gupta, Boris Dimitrov Andreev
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Patent number: 11749537Abstract: Electronic device processing assemblies including an EFEM with at least one side storage pod attached thereto. The side storage pod has a side storage pod container. A supply conduit extends between an upper plenum of the EFEM to the side storage pod container. A fan causes purge gas to simultaneously flow into the EFEM chamber and into the side storage pod container. The fan also causes recirculation of the purge gas from the EFEM chamber. Methods of operating EFEMs and EFEMs are also disclosed.Type: GrantFiled: October 18, 2019Date of Patent: September 5, 2023Assignee: Applied Materials, Inc.Inventors: Patrick Pannese, Murali Narasimhan, Paul B. Reuter, Nir Merry
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Patent number: 11569102Abstract: A method includes flowing gas comprising an oxidation inhibiting gas into a chamber of a semiconductor processing system. The chamber includes one or more of a factory interface of the semiconductor processing system or an adjacent chamber that is mounted to the factory interface. The method further includes receiving, via one or more sensors coupled to the chamber, sensor data indicating at least one of a current oxygen level within the chamber or a current moisture level within the chamber. The method further includes determining, based on the sensor data, whether to perform an adjustment of a current amount of the oxidation inhibiting gas entering into the chamber. The method further includes, responsive to determining to perform the adjustment, causing the adjustment of the current amount of the oxidation inhibiting gas entering into the chamber.Type: GrantFiled: February 14, 2020Date of Patent: January 31, 2023Assignee: Applied Materials, Inc.Inventors: Murali Narasimhan, Patrick Pannese, Kunal Jain
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Patent number: 11244844Abstract: In some embodiments, a side storage pod apparatus of an equipment front end module (EFEM) includes a side storage enclosure having a surface configured to couple to a side wall of a body of the equipment front end module, and an opening configured to receive substrates from the equipment front end module. The EFEM further includes a side storage chamber within the side storage enclosure having a plurality of support members configured to support substrates thereon. The EFEM further includes a plenum chamber provided proximate the side storage chamber, the plenum chamber being a separate chamber from the side storage chamber and an exhaust port coupled to the plenum chamber.Type: GrantFiled: October 18, 2019Date of Patent: February 8, 2022Assignee: Applied Materials, Inc.Inventors: Paul B. Reuter, Murali Narasimhan, Amulya L. Athayde, Patrick Pannese, Dean C. Hruzek, Nir Merry
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Publication number: 20210257233Abstract: A method includes flowing gas comprising an oxidation inhibiting gas into a chamber of a semiconductor processing system. The chamber includes one or more of a factory interface of the semiconductor processing system or an adjacent chamber that is mounted to the factory interface. The method further includes receiving, via one or more sensors coupled to the chamber, sensor data indicating at least one of a current oxygen level within the chamber or a current moisture level within the chamber. The method further includes determining, based on the sensor data, whether to perform an adjustment of a current amount of the oxidation inhibiting gas entering into the chamber. The method further includes, responsive to determining to perform the adjustment, causing the adjustment of the current amount of the oxidation inhibiting gas entering into the chamber.Type: ApplicationFiled: February 14, 2020Publication date: August 19, 2021Inventors: Murali Narasimhan, Patrick Pannese, Kunal Jain
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Publication number: 20200135499Abstract: Electronic device processing assemblies including an EFEM with at least one side storage pod attached thereto. The side storage pod has a side storage pod container. A supply conduit extends between an upper plenum of the EFEM to the side storage pod container. A fan causes purge gas to simultaneously flow into the EFEM chamber and into the side storage pod container. The fan also causes recirculation of the purge gas from the EFEM chamber. Methods of operating EFEMs and EFEMs are also disclosed.Type: ApplicationFiled: October 18, 2019Publication date: April 30, 2020Inventors: Patrick Pannese, Murali Narasimhan, Paul B. Reuter, Nir Merry
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Publication number: 20200135521Abstract: In some embodiments, a side storage pod apparatus of an equipment front end module (EFEM) includes a side storage enclosure having a surface configured to couple to a side wall of a body of the equipment front end module, and an opening configured to receive substrates from the equipment front end module. The EFEM further includes a side storage chamber within the side storage enclosure having a plurality of support members configured to support substrates thereon. The EFEM further includes a plenum chamber provided proximate the side storage chamber, the plenum chamber being a separate chamber from the side storage chamber and an exhaust port coupled to the plenum chamber.Type: ApplicationFiled: October 18, 2019Publication date: April 30, 2020Inventors: Paul B. Reuter, Murali Narasimhan, Amulya L. Athayde, Patrick Pannese, Dean C. Hruzek, Nir Merry
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Patent number: 9305838Abstract: An integrated circuit with BEOL interconnects may comprise: a substrate including a semiconductor device; a first layer of dielectric over the surface of the substrate, the first layer of dielectric including a filled via for making electrical contact to the semiconductor device; and a second layer of dielectric on the first layer of dielectric, the second layer of dielectric including a trench running perpendicular to the longitudinal axis of the filled via, the trench being filled with an interconnect line, the interconnect line comprising cross-linked carbon nanotubes and being physically and electrically connected to the filled via. Cross-linked CNTs are grown on catalyst particles on the bottom of the trench using growth conditions including a partial pressure of precursor gas greater than the transition partial pressure at which carbon nanotube growth transitions from a parallel carbon nanotube growth mode to a cross-linked carbon nanotube growth mode.Type: GrantFiled: August 31, 2012Date of Patent: April 5, 2016Assignee: Applied Materials, Inc.Inventors: Pravin K. Narwankar, Joe Griffith Cruz, Arvind Sundarrajan, Murali Narasimhan, Subbalakshmi Sreekala, Victor Pushparaj
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Publication number: 20130228933Abstract: An integrated circuit with BEOL interconnects may comprise: a substrate including a semiconductor device; a first layer of dielectric over the surface of the substrate, the first layer of dielectric including a filled via for making electrical contact to the semiconductor device; and a second layer of dielectric on the first layer of dielectric, the second layer of dielectric including a trench running perpendicular to the longitudinal axis of the filled via, the trench being filled with an interconnect line, the interconnect line comprising cross-linked carbon nanotubes and being physically and electrically connected to the filled via. Cross-linked CNTs are grown on catalyst particles on the bottom of the trench using growth conditions including a partial pressure of precursor gas greater than the transition partial pressure at which carbon nanotube growth transitions from a parallel carbon nanotube growth mode to a cross-linked carbon nanotube growth mode.Type: ApplicationFiled: August 31, 2012Publication date: September 5, 2013Applicant: Applied Materials, Inc.Inventors: Pravin K. Narwankar, Joe Griffith Cruz, Arvind Sundarrajan, Murali Narasimhan, Subbalakshmi Sreekala, Victor Pushparaj
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Publication number: 20120225558Abstract: Methods and apparatus for removing oxide from a surface, the surface comprising at least one of silicon and germanium, are provided. The method and apparatus are particularly suitable for removing native oxide from a metal silicide layer of a contact structure. The method and apparatus advantageously integrate both the etch stop layer etching process and the native oxide removal process in a single chamber, thereby eliminating native oxide growth or other contaminates redeposit during the substrate transfer processes. Furthermore, the method and the apparatus also provides the improved three-step chemical reaction process to efficiently remove native oxide from the metal silicide layer without adversely altering the geometry of the contact structure and the critical dimension of the trenches or vias formed in the contact structure.Type: ApplicationFiled: March 2, 2012Publication date: September 6, 2012Applicant: APPLIED MATERIALS, INCInventors: MEI CHANG, Linh Thanh, Bo Zheng, Arvind Sundarrajan, John C. Forster, Umesh M. Kellkar, Murali Narasimhan
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Publication number: 20020182887Abstract: The present invention generally provides a method and apparatus for forming a doped layer on a substrate to improve uniformity of subsequent deposition thereover. Preferably, the layer is deposited by a sputtering process, such as physical vapor deposition (PVD) or Ionized Metal Plasma (IMP) PVD, using a doped target of conductive material. Preferably, the conductive material, such as copper, is alloyed with a dopant, such as phosphorus, boron, indium, tin, beryllium, or combinations thereof, to improve deposition uniformity of the doped layer over the substrate surface and to reduce oxidation of the conductive material. It is believed that the addition of a dopant, such as phosphorus, stabilizes the conductive material surface, such as a copper surface, and lessens the surface diffusivity of the conductive material.Type: ApplicationFiled: July 16, 2002Publication date: December 5, 2002Applicant: Applied Materials, Inc.Inventors: Vikram Pavate, Murali Narasimhan
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Patent number: 6432819Abstract: The present invention generally provides a method and apparatus for forming a doped layer on a substrate to improve uniformity of subsequent deposition thereover. Preferably, the layer is deposited by a sputtering process, such as physical vapor deposition (PVD) or Ionized Metal Plasma (IMP) PVD, using a doped target of conductive material. Preferably, the conductive material, such as copper, is alloyed with a dopant, such as phosphorus, boron, indium, tin, beryllium, or combinations thereof, to improve deposition uniformity of the doped layer over the substrate surface and to reduce oxidation of the conductive material. It is believed that the addition of a dopant, such as phosphorus, stabilizes the conductive material surface, such as a copper surface, and lessens the surface diffusivity of the conductive material.Type: GrantFiled: September 27, 1999Date of Patent: August 13, 2002Assignee: Applied Materials, Inc.Inventors: Vikram Pavate, Murali Narasimhan
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Publication number: 20020102365Abstract: The present invention generally provides a method for stabilizing a halogen-doped silicon oxide film, particularly a fluorinated silicon oxide film. The invention also provides a method for preventing loosely bonded halogen atoms from reacting with components of the barrier layer during subsequent processing of the substrate. The invention provides a hydrogen plasma treatment of the halogen-doped silicon oxide film without subjecting the substrate to a heated environment that may damage the substrate and the structures formed on the substrate. The invention also improves the adhesion strength between the halogen-doped silicon oxide film and the barrier layer. Furthermore, the hydrogen plasma treatment can be practiced in a variety of plasma processing chambers of an integrated process sequence, including pre-clean chambers, physical vapor deposition chambers, chemical vapor deposition chambers, etch chambers and other plasma processing chambers.Type: ApplicationFiled: March 12, 2002Publication date: August 1, 2002Applicant: Applied Materials, Inc.Inventors: Murali Narasimhan, Vikram Pavate, Kenny King-Tai Ngan, Xiangbing Li
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Publication number: 20020093101Abstract: A method of metallization comprising forming a conductive layer comprising nickel and vanadium inside an opening. The conductive layer comprising nickel and vanadium can be used as a barrier layer to prevent interlayer metal diffusion. Alternatively, the conductive layer can also be used as a seed layer for subsequent metal electroplating. In one embodiment, the conductive layer is used as an integrated barrier and seed layer for subsequent copper plating for submicron applications.Type: ApplicationFiled: June 13, 2001Publication date: July 18, 2002Inventors: Subramoney Iyer, Murali Narasimhan, Murali Abburi, Vijayashree Subramanyam
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Publication number: 20020088716Abstract: The present invention provides a method and apparatus for forming a copper layer on a substrate, preferably using a sputtering process. The sputtering process involves bombarding a conductive member of enhanced hardness with ions to dislodge the copper from the conductive member. The hardness of the target may be enhanced by alloying the copper conductive member with another material and/or mechanically working the material of the conductive member during its manufacturing process in order to improve conductive member and film qualities. The copper may be alloyed with magnesium, zinc, aluminum, iron, nickel, silicon and any combination thereof.Type: ApplicationFiled: March 6, 2002Publication date: July 11, 2002Inventors: Vikram Pavate, Murali Abburi, Murali Narasimhan, Seshadri Ramaswami
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Patent number: 6391163Abstract: The present invention provides a method and apparatus for forming a copper layer on a substrate, preferably using a sputtering process. The sputtering process involves bombarding a conductive member of enhanced hardness with ions to dislodge the copper from the conductive member. The hardness of the target may be enhanced by alloying the copper conductive member with another material and/or mechanically working the material of the conductive member during its manufacturing process in order to improve conductive member and film qualities. The copper may be alloyed with magnesium, zinc, aluminum, iron, nickel, silicon and any combination thereof.Type: GrantFiled: March 2, 2000Date of Patent: May 21, 2002Assignee: Applied Materials, Inc.Inventors: Vikram Pavate, Murali Abburi, Murali Narasimhan, Seshadri Ramaswami
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Publication number: 20020047116Abstract: Coils for use within high density plasma chambers are provided that do not electrically disconnect or short circuit following repeated depositions and that produce films having reduced in-film defect densities. To reduce in-film defect densities, dielectric inclusion content, porosity, grain size and surface roughness of a coil are reduced, while the mechanical strength of the coil is increased so as to both decrease defect generation and thermal creep rate (e.g., to prevent electrical disconnection or short circuiting of the coil following repeated depositions).Type: ApplicationFiled: September 28, 2001Publication date: April 25, 2002Inventors: Vikram Pavate, Murali Narasimhan
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Patent number: 6372301Abstract: The present invention generally provides a method for stabilizing a halogen-doped silicon oxide film, particularly a fluorinated silicon oxide film. The invention also provides a method for preventing loosely bonded halogen atoms from reacting with components of the barrier layer during subsequent processing of the substrate. The invention provides a hydrogen plasma treatment of the halogen-doped silicon oxide film without subjecting the substrate to a heated environment that may damage the substrate and the structures formed on the substrate. The invention also improves the adhesion strength between the halogen-doped silicon oxide film and the barrier layer. Furthermore, the hydrogen plasma treatment can be practiced in a variety of plasma processing chambers of an integrated process sequence, including pre-clean chambers, physical vapor deposition chambers, chemical vapor deposition chambers, etch chambers and other plasma processing chambers.Type: GrantFiled: December 22, 1998Date of Patent: April 16, 2002Assignee: Applied Materials, Inc.Inventors: Murali Narasimhan, Vikram Pavate, Kenny King-Tai Ngan, Xiangbing Li
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Patent number: 6315872Abstract: Coils for use within high density plasma chambers are provided that do not electrically disconnect or short circuit following repeated depositions and that produce films having reduced in-film defect densities. To reduce in-film defect densities, dielectric inclusion content, porosity, grain size and surface roughness of a coil are reduced, while the mechanical strength of the coil is increased so as to both decrease defect generation and thermal creep rate (e.g., to prevent electrical disconnection or short circuiting of the coil following repeated depositions).Type: GrantFiled: October 8, 1999Date of Patent: November 13, 2001Assignee: Applied Materials, Inc.Inventors: Vikram Pavate, Murali Narasimhan
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Patent number: 6277253Abstract: Embodiments include a method for depositing material onto a workpiece in a sputtering chamber. The method includes sputtering a target and a coil in said sputtering chamber. The coil may have a preformed multilayer structure formed outside of the sputtering chamber. The outer layer of the coil may act as a secondary source of deposition material. The multilayer structure may be formed with an inner region or a base metal and an outer layer of a sputtering metal. The outer layer may be formed using a process such as plasma spraying, arc spraying, flame spraying, ion plating, chemical vapor deposition and electroplating.Type: GrantFiled: October 6, 1999Date of Patent: August 21, 2001Assignee: Applied Materials, Inc.Inventors: Murali Narasimhan, Xiangbing Li