Abstract: Methods, systems, and devices for self-aligned techniques for forming connections in a memory device are described. A redistribution layer (RDL) for coupling an electrode of a capacitor of a memory cell with a corresponding selector device may be fabricated at a same time or stage as the electrode, using self-aligned techniques. When forming portions of a memory cell, a cavity for the electrode may be etched, and a portion of the RDL that extends from the electrode cavity to a corresponding selector device may also be selectively etched. The resulting cavities may be filled with an electrode material, which may form the electrode and couple the electrode to the corresponding selector device. The resulting memory device may support implementation of a staggered configuration for memory cells, and may include electrodes that share a crystalline structure with one or more corresponding portions of an RDL.

Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode.

Abstract: Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A capacitor is electrically coupled to the second source/drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region. The non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.

Abstract: Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A capacitor is electrically coupled to the second source/drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region. The non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.

Abstract: Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A capacitor is electrically coupled to the second source/drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region. The non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.

Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode.

Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode.

Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode.

Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode.

Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode.

Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode.

Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode.

Abstract: Exemplary embodiments of the present invention are directed towards a method for fabricating a semiconductor memory device comprising selectively depositing a material to form a cap above a recessed cell structure in order to prevent degradation of components inside the cell structure in oxidative or corrosive environments.

Abstract: Exemplary embodiments of the present invention are directed towards a method for fabricating a semiconductor memory device comprising selectively depositing a material to form a cap above a recessed cell structure in order to prevent degradation of components inside the cell structure in oxidative or corrosive environments.

Abstract: A method of forming a resistive memory element comprises forming an oxide material over a first electrode. The oxide material is exposed to a plasma process to form a treated oxide material. A second electrode is formed on the treated oxide material. Additional methods of forming a resistive memory element, as well as related resistive memory elements, resistive memory cells, and resistive memory devices are also described.

Abstract: Exemplary embodiments of the present invention are directed towards a method for fabricating a semiconductor memory device comprising selectively depositing a material to form a cap above a recessed cell structure in order to prevent degradation of components inside the cell structure in oxidative or corrosive environments.

Abstract: A method of forming a resistive memory element comprises forming an oxide material over a first electrode. The oxide material is exposed to a plasma process to form a treated oxide material. A second electrode is formed on the treated oxide material. Additional methods of forming a resistive memory element, as well as related resistive memory elements, resistive memory cells, and resistive memory devices are also described.

Abstract: A method of forming a resistive memory element comprises forming an oxide material over a first electrode. The oxide material is exposed to a plasma process to form a treated oxide material. A second electrode is formed on the treated oxide material. Additional methods of forming a resistive memory element, as well as related resistive memory elements, resistive memory cells, and resistive memory devices are also described.

Abstract: An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die having an address switch; a bottom electrode contact, free of halogen constituents, characteristic of a chemical vapor deposition or an atomic layer deposition, and coupled to the address switch; a transition material layer directly on the bottom electrode contact; and a top electrode contact, directly on the transition material layer, for forming a non-volatile memory array on the integrated circuit die.

Abstract: A resistive sense memory cell includes a layer of crystalline praseodymium calcium manganese oxide and a layer of amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack. A first and second electrode are separated by the resistive sense memory stack. The resistive sense memory cell can further include an oxygen diffusion barrier layer separating the layer of crystalline praseodymium calcium manganese oxide from the layer of amorphous praseodymium calcium manganese oxide a layer. Methods include depositing an amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack.