Patents by Inventor Muthukumar P. Swaminathan
Muthukumar P. Swaminathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11074188Abstract: A two-level main memory that includes a persistent memory and a cache is provided. Locations of dirty cache lines in the cache are tracked through the use a dirty cache line tracker. The dirty cache line tracker is stored in the cache and can be cached in a memory controller for the persistent memory. The dirty cache line tracker can be used to bypass cache lookup, perform efficient dirty cache line scrubbing and to decouple battery power and capacity of the cache in the two-level main memory.Type: GrantFiled: February 18, 2019Date of Patent: July 27, 2021Assignee: Intel CorporationInventors: Zhe Wang, Alaa R. Alameldeen, Lidia Warnes, Andy M. Rudoff, Muthukumar P. Swaminathan
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Publication number: 20210011706Abstract: Examples include updating firmware for a persistent memory module in a computing system during runtime. Examples include copying a new version of persistent memory module firmware into an available area of random-access memory (RAM) in the persistent memory module, and transferring processing of a current version of persistent memory module firmware to the new version of persistent memory module firmware during runtime of the computing system, without a reset of the computing system and without quiesce of access to persistent memory media in the persistent memory module, while continuing to perform critical event handling by the current version of persistent memory module firmware.Type: ApplicationFiled: September 24, 2020Publication date: January 14, 2021Inventors: Murugasamy K. NACHIMUTHU, Mohan J. KUMAR, Muthukumar P. SWAMINATHAN, Daniel K. OSAWA, Maciej PLUCINSKI
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Patent number: 10719443Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: GrantFiled: March 25, 2019Date of Patent: July 21, 2020Assignee: Intel CorporationInventors: Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman, Muthukumar P. Swaminathan, Dimitrios Ziakas, Mohan J. Kumar, Bassam N. Coury, Glenn J. Hinton
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Patent number: 10691626Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.Type: GrantFiled: May 7, 2019Date of Patent: June 23, 2020Assignee: Intel CorporationInventors: Bill Nale, Raj K. Ramanujan, Muthukumar P. Swaminathan, Tessil Thomas, Taarinya Polepeddi
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Patent number: 10678315Abstract: Data reliability and integrity may be compromised when memory resources used to store the data reach elevated temperatures. A sensor in the memory resource may monitor the temperature of the memory resource in real-time. A comparator in the memory resource may indicate a high temperature condition to a memory controller. The memory controller, in response to the high temperature condition, can restrict or halt data flow to the memory resource. When the real-time temperature of the memory resource falls below a defined threshold, the memory controller may resume data flow to the memory resource.Type: GrantFiled: October 1, 2018Date of Patent: June 9, 2020Assignee: Intel CorporationInventors: Rajesh Sundaram, Muthukumar P. Swaminathan, Doyle Rivers
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Publication number: 20200133578Abstract: Technologies for issuing commands on selected memory devices includes an apparatus that includes a data storage controller and multiple non-volatile, write in place, byte or block addressable memory devices. The memory devices are arranged in one or more ranks, and the memory devices in each rank are connected to a same communication channel. The data storage controller is to select a subgroup of the plurality of the memory devices in a rank without modifying an identifier of each memory device, and issue a command to operate on data of the selected subgroup.Type: ApplicationFiled: October 29, 2019Publication date: April 30, 2020Inventors: Muthukumar P. Swaminathan, Kunal A. Khochare
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Publication number: 20190332556Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology.Type: ApplicationFiled: May 7, 2019Publication date: October 31, 2019Inventors: Bill NALE, Raj K. RAMANUJAN, Muthukumar P. SWAMINATHAN, Tessil THOMAS, Taarinya POLEPEDDI
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Patent number: 10459659Abstract: Technologies for issuing commands on selected memory devices includes an apparatus that includes a data storage controller and multiple non-volatile, write in place, byte or block addressable memory devices. The memory devices are arranged in one or more ranks, and the memory devices in each rank are connected to a same communication channel. The data storage controller is to select a subgroup of the plurality of the memory devices in a rank without modifying an identifier of each memory device, and issue a command to operate on data of the selected subgroup.Type: GrantFiled: March 31, 2017Date of Patent: October 29, 2019Assignee: Intel CorporationInventors: Muthukumar P. Swaminathan, Kunal A. Khochare
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Patent number: 10452312Abstract: Provided are an apparatus, system and method to determine whether to use a low or high read voltage. First level indications of write addresses, for locations in the non-volatile memory to which write requests have been directed, are included in a first level data structure. For a write address of the write addresses having a first level indication in the first level data structure, the first level indication of the write address is removed from the first level data structure and a second level indication for the write address is added to a second level data structure to free space in the first level data structure to indicate a further write address. A first voltage level is used to read data from read addresses mapping to one of the first and second level indications in the first and the second level data structures, respectively.Type: GrantFiled: December 30, 2016Date of Patent: October 22, 2019Assignee: INTEL CORPORATIONInventors: Zhe Wang, Zeshan A. Chishti, Muthukumar P. Swaminathan, Alaa R. Alameldeen, Kunal A. Khochare, Jason A. Gayman
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Publication number: 20190220406Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: ApplicationFiled: March 25, 2019Publication date: July 18, 2019Inventors: Raj K. RAMANUJAN, Rajat AGARWAL, Kai CHENG, Taarinya POLEPEDDI, Camille C. RAAD, David J. ZIMMERMAN, Muthukumar P. SWAMINATHAN, Dimitrios ZIAKAS, Mohan J. KUMAR, Bassam N. COURY, Glenn J. HINTON
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Publication number: 20190179764Abstract: A two-level main memory that includes a persistent memory and a cache is provided. Locations of dirty cache lines in the cache are tracked through the use a dirty cache line tracker. The dirty cache line tracker is stored in the cache and can be cached in a memory controller for the persistent memory. The dirty cache line tracker can be used to bypass cache lookup, perform efficient dirty cache line scrubbing and to decouple battery power and capacity of the cache in the two-level main memory.Type: ApplicationFiled: February 18, 2019Publication date: June 13, 2019Inventors: Zhe WANG, Alaa R. ALAMELDEEN, Lidia WARNES, Andy M. RUDOFF, Muthukumar P. SWAMINATHAN
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Patent number: 10310989Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller memory; a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a current timer index from a timer circuitry in response to an initiation of a periodic patrol scrub and to compare the current timer index to a stored timestamp. The VDM selection circuitry is to update a state of a sub-block of a memory array, if the state is less than a threshold and a difference between the current timer index and the stored timestamp is nonzero. The timestamp circuitry is further to store the current timer index as a new timestamp.Type: GrantFiled: September 29, 2017Date of Patent: June 4, 2019Assignee: Intel CorporationInventors: Philip Hillier, Jeffrey W. Ryden, Muthukumar P. Swaminathan, Zion S. Kwok, Kunal A. Khochare, Richard P. Mangold, Prashant S. Damle
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Patent number: 10282323Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.Type: GrantFiled: July 26, 2018Date of Patent: May 7, 2019Assignee: Intel CorporationInventors: Bill Nale, Raj K. Ramanujan, Muthukumar P. Swaminathan, Tessil Thomas, Taarinya Polepeddi
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Publication number: 20190107871Abstract: Data reliability and integrity may be compromised when memory resources used to store the data reach elevated temperatures. A sensor in the memory resource may monitor the temperature of the memory resource in real-time. A comparator in the memory resource may indicate a high temperature condition to a memory controller. The memory controller, in response to the high temperature condition, can restrict or halt data flow to the memory resource. When the real-time temperature of the memory resource falls below a defined threshold, the memory controller may resume data flow to the memory resource.Type: ApplicationFiled: October 1, 2018Publication date: April 11, 2019Applicant: Intel CorporationInventors: RAJESH SUNDARAM, MUTHUKUMAR P. SWAMINATHAN, DOYLE RIVERS
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Publication number: 20190102320Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller memory; a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a current timer index from a timer circuitry in response to an initiation of a periodic patrol scrub and to compare the current timer index to a stored timestamp. The VDM selection circuitry is to update a state of a sub-block of a memory array, if the state is less than a threshold and a difference between the current timer index and the stored timestamp is nonzero. The timestamp circuitry is further to store the current timer index as a new timestamp.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Applicant: INTEL CORPORATIONInventors: Philip Hillier, Jeffrey W. Ryden, Muthukumar P. Swaminathan, Zion S. Kwok, Kunal A. Khochare, Richard P. Mangold, Prashant S. Damle
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Patent number: 10241943Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology.Type: GrantFiled: December 29, 2017Date of Patent: March 26, 2019Assignee: Intel CorporationInventors: Bill Nale, Raj K. Ramanujan, Muthukumar P. Swaminathan, Tessil Thomas, Taarinya Polepeddi
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Patent number: 10241912Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: GrantFiled: March 13, 2017Date of Patent: March 26, 2019Assignee: Intel CorporationInventors: Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman, Muthukumar P. Swaminathan, Dimitrios Ziakas, Mohan J. Kumar, Bassam N. Coury, Glenn J. Hinton
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Publication number: 20190042445Abstract: Technologies for caching persistent two-level memory (2LM) data include a memory and a processor. The memory includes a volatile memory device and a non-volatile memory device. The processor determines a persistent memory address space for persistent 2LM data and determines one or more non-volatile memory devices that the persistent memory address space is mapped to. The processor further configures the persistent memory address space of the non-volatile memory device to operate in a persistent 2LM mode and further configures an operating system to cache accesses to persistent memory address space in volatile memory.Type: ApplicationFiled: August 7, 2017Publication date: February 7, 2019Inventors: Muthukumar P. Swaminathan, Murugasamy K. Nachimuthu, Mahesh S. Natu
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Publication number: 20190018809Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology.Type: ApplicationFiled: July 26, 2018Publication date: January 17, 2019Inventors: Bill NALE, Raj K. RAMANUJAN, Muthukumar P. SWAMINATHAN, Tessil THOMAS, Taarinya POLEPEDDI
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Publication number: 20180285020Abstract: Technologies for issuing commands on selected memory devices includes an apparatus that includes a data storage controller and multiple non-volatile, write in place, byte or block addressable memory devices. The memory devices are arranged in one or more ranks, and the memory devices in each rank are connected to a same communication channel. The data storage controller is to select a subgroup of the plurality of the memory devices in a rank without modifying an identifier of each memory device, and issue a command to operate on data of the selected subgroup.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Inventors: Muthukumar P. Swaminathan, Kunal A. Khochare